pkt_bytes_to_words.sv (3460B)
1 // Copyright 2014 Brian Swetland <swetland@frotz.net> 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 `timescale 1ns / 1ps 16 17 18 // converts packet bytestream to wordstream 19 // 20 // input: rxdata accepted when rxvalid=1 21 // rxeop terminates stream 22 // rxeop may not happen on same clock as rxvalid 23 // output: data and bytecount presented with valid=1 24 // eop=1 indicates end of stream 25 // err=1 indicates crc error (on clock where eop==1) 26 // eop and valid will not happen on the same clock 27 28 module pkt_bytes_to_words( 29 input clk, 30 input [7:0]rxdata, 31 input rxvalid, 32 input rxeop, 33 34 output [31:0]data, 35 output [11:0]bytecount, 36 output reg valid = 0, 37 output reg eop = 0, 38 output reg err = 0 39 ); 40 41 parameter WITH_CRC_CHECK = 1; 42 43 wire crc_err; 44 45 generate if (WITH_CRC_CHECK) begin 46 wire [31:0]crc; 47 48 eth_crc32 crc0( 49 .clk(clk), 50 .en(rxvalid), 51 .rst(eop), 52 .dat(rxdata), 53 .crc(crc) 54 ); 55 56 assign crc_err = (crc != 32'hdebb20e3); 57 end else begin 58 assign crc_err = 0; 59 end endgenerate 60 61 typedef enum { IDLE, BYTE0, BYTE1, BYTE2, BYTE3, EOP } state_t; 62 state_t state = IDLE; 63 state_t next_state; 64 65 reg [11:0]count = 0; 66 wire [11:0]count_plus_one = (count + 1); 67 reg [11:0]next_count; 68 reg [7:0]byte0 = 0; 69 reg [7:0]next_byte0; 70 reg [7:0]byte1 = 0; 71 reg [7:0]next_byte1; 72 reg [7:0]byte2 = 0; 73 reg [7:0]next_byte2; 74 reg [7:0]byte3 = 0; 75 reg [7:0]next_byte3; 76 77 reg next_valid; 78 reg next_eop; 79 80 assign data = { byte3, byte2, byte1, byte0 }; 81 assign bytecount = count; 82 83 always_comb begin 84 next_state = state; 85 next_count = count; 86 next_byte0 = byte0; 87 next_byte1 = byte1; 88 next_byte2 = byte2; 89 next_byte3 = byte3; 90 next_valid = 0; 91 next_eop = 0; 92 93 case (state) 94 IDLE: begin 95 if (rxvalid) begin 96 next_state = BYTE0; 97 next_byte0 = rxdata; 98 next_byte1 = 0; 99 next_byte2 = 0; 100 next_byte3 = 0; 101 next_count = 1; 102 end 103 end 104 BYTE0: begin 105 if (rxvalid) begin 106 next_state = BYTE1; 107 next_byte1 = rxdata; 108 next_count = count_plus_one; 109 end else if (rxeop) begin 110 next_state = EOP; 111 next_valid = 1; 112 end 113 end 114 BYTE1: begin 115 if (rxvalid) begin 116 next_state = BYTE2; 117 next_byte2 = rxdata; 118 next_count = count_plus_one; 119 end else if (rxeop) begin 120 next_state = EOP; 121 next_valid = 1; 122 end 123 end 124 BYTE2: begin 125 if (rxvalid) begin 126 next_state = BYTE3; 127 next_byte3 = rxdata; 128 next_count = count_plus_one; 129 next_valid = 1; 130 end else if (rxeop) begin 131 next_state = EOP; 132 next_valid = 1; 133 end 134 end 135 BYTE3: begin 136 if (rxvalid) begin 137 next_state = BYTE0; 138 next_byte0 = rxdata; 139 next_byte1 = 0; 140 next_byte2 = 0; 141 next_byte3 = 0; 142 next_count = count_plus_one; 143 end else if (rxeop) begin 144 next_state = EOP; 145 end 146 end 147 EOP: begin 148 next_state = IDLE; 149 next_eop = 1; 150 end 151 endcase 152 end 153 154 always_ff @(posedge clk) begin 155 state <= next_state; 156 count <= next_count; 157 byte0 <= next_byte0; 158 byte1 <= next_byte1; 159 byte2 <= next_byte2; 160 byte3 <= next_byte3; 161 valid <= next_valid; 162 eop <= next_eop; 163 err <= crc_err; 164 end 165 166 endmodule