zynq-sandbox

old FPGA projects for ZYNQ
git clone http://frotz.net/git/zynq-sandbox.git
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reg_ifc.sv (1209B)


      1 // Copyright 2014 Brian Swetland <swetland@frotz.net>
      2 //
      3 // Licensed under the Apache License, Version 2.0 (the "License");
      4 // you may not use this file except in compliance with the License.
      5 // You may obtain a copy of the License at
      6 //
      7 //     http://www.apache.org/licenses/LICENSE-2.0
      8 //
      9 // Unless required by applicable law or agreed to in writing, software
     10 // distributed under the License is distributed on an "AS IS" BASIS,
     11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
     12 // See the License for the specific language governing permissions and
     13 // limitations under the License.
     14 
     15 `timescale 1ns/1ps
     16 
     17 // write:
     18 //   slave samples wr, waddr, wdata on posedge clk
     19 //   if wr==1, wdata written to waddr
     20 // read:
     21 //   slave samples rd, raddr on posedge clk
     22 //   if rd==1, read is requested
     23 //   master samples rdata on next posedge clk 
     24 
     25 interface reg_ifc;
     26 
     27 parameter AWIDTH = 2;
     28 parameter DWIDTH = 32;
     29 
     30 logic [AWIDTH-1:0]raddr;
     31 logic [AWIDTH-1:0]waddr;
     32 logic rd;
     33 logic wr;
     34 logic [DWIDTH-1:0]rdata;
     35 logic [DWIDTH-1:0]wdata;
     36 
     37 modport master (
     38 	output raddr, waddr, rd, wr, wdata,
     39 	input rdata
     40 	);
     41 
     42 modport slave (
     43 	input raddr, waddr, rd, wr, wdata,
     44 	output rdata
     45 	);
     46 
     47 endinterface