zynq-sandbox

old FPGA projects for ZYNQ
git clone http://frotz.net/git/zynq-sandbox.git
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serdes_8to1_tx.sv (696B)

      1 `timescale 1ns / 1ps
      2 
      3 module serdes_8to1_tx(
      4 	input clk,
      5 	input clkx4,
      6 	input reset,
      7 	output o_p,
      8 	output o_n,
      9 	input [7:0]i_data
     10 	);
     11 
     12 wire out;
     13 
     14 OBUFDS bufds(.I(out), .O(o_p), .OB(o_n));
     15 
     16 OSERDESE2 #(
     17 	.DATA_RATE_OQ("DDR"),
     18 	.DATA_RATE_TQ("SDR"),
     19 	.DATA_WIDTH(8),
     20 	.TRISTATE_WIDTH(1),
     21 	.SERDES_MODE("MASTER"),
     22 	)serdes_lo(
     23 	.CLK(clkx4),
     24 	.CLKDIV(clk),
     25 	.D1(i_data[0]),
     26 	.D2(i_data[1]),
     27 	.D3(i_data[2]),
     28 	.D4(i_data[3]),
     29 	.D5(i_data[4]),
     30 	.D6(i_data[5]),
     31 	.D7(i_data[6]),
     32 	.D8(i_data[7]),
     33 	.OCE(1),
     34 	.OFB(),
     35 	.OQ(out),
     36 	.RST(reset),
     37 	.SHIFTIN1(),
     38 	.SHIFTIN2(),
     39 	.SHIFTOUT1(),
     40 	.SHIFTOUT2(),
     41 	.TBYTEIN(0),
     42 	.TBYTEOUT(),
     43 	.TCE(0),
     44 	.TFB(),
     45 	.TQ(),
     46 	.T1(0),
     47 	.T2(0),
     48 	.T3(0),
     49 	.T4(0)
     50 	);
     51 
     52 endmodule