sync_oneway.sv (1134B)
1 // Copyright 2014 Brian Swetland <swetland@frotz.net> 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 `timescale 1ns / 1ps 16 17 (* keep_hierarchy = "yes" *) 18 module sync_oneway( 19 input txclk, 20 input txdat, 21 input rxclk, 22 output rxdat 23 ); 24 25 reg a = 0; 26 27 // Mark as ASYNC_REG to ensure they are not optimized away, are adjacent 28 // (same slice), and inform // xilinx simulation tools that they're being 29 // used for synchronization. 30 // See UG912 Vivado Properties 31 (* ASYNC_REG = "TRUE" *) 32 reg b = 0, c = 0; 33 34 always_ff @(posedge txclk) 35 a <= txdat; 36 37 always_ff @(posedge rxclk) begin 38 b <= a; 39 c <= b; 40 end 41 42 assign rxdat = c; 43 44 endmodule