eth_capture_test.sv (1827B)
1 // Copyright 2014 Brian Swetland <swetland@frotz.net> 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 `timescale 1ns / 1ps 16 17 `ifdef verilator 18 module testbench(input clk); 19 `else 20 module testbench(); 21 reg clk = 0; 22 always #5 clk = ~clk; 23 `endif 24 25 reg clk50 = 0; 26 always @(posedge clk) 27 clk50 = ~clk50; 28 29 wire [1:0]eth_dat; 30 wire eth_pkt; 31 wire done; 32 33 reg pkt_gen_start = 0; 34 35 eth_packet_gen #( 36 .PACKET_COUNT(5), 37 .PACKET_LENGTH(277) 38 ) pgen0 ( 39 .clk50(clk50), 40 .data(eth_dat), 41 .packet(eth_pkt), 42 .start(pkt_gen_start), 43 .done(done) 44 ); 45 46 wire [7:0]rxdata; 47 wire rxvalid; 48 wire rxeop; 49 wire rxsop; 50 51 eth_rmii_rx rx0( 52 .clk50(clk50), 53 .rx(eth_dat), 54 .crs_dv(eth_pkt), 55 .data(rxdata), 56 .valid(rxvalid), 57 .eop(rxeop), 58 .sop(rxsop), 59 .out_tx(), 60 .out_txen() 61 ); 62 63 axi_ifc #(.AXI3(1)) axi_dma(); 64 65 reg cap_reset = 0; 66 67 eth_capture cap0( 68 .clk50(clk50), 69 .rxsop(rxsop), 70 .rxeop(rxeop), 71 .rxdata(rxdata), 72 .rxvalid(rxvalid), 73 .clk(clk), 74 .reset(cap_reset), 75 .enable(1), 76 .axi_dma(axi_dma) 77 ); 78 79 axi_sram sram0( 80 .clk(clk), 81 .s(axi_dma) 82 ); 83 84 `ifdef XX 85 always @(posedge clk50) 86 if (done) 87 $finish; 88 `endif 89 90 reg [31:0]evt_cnt = 0; 91 always @(posedge clk) begin 92 evt_cnt <= evt_cnt + 1; 93 if (evt_cnt == 150) cap_reset <= 1; 94 if (evt_cnt == 151) cap_reset <= 0; 95 if (evt_cnt == 200) pkt_gen_start <= 1; 96 if (evt_cnt == 100000) $finish; 97 end 98 99 endmodule