eth_crc32_test.sv (805B)
1 `timescale 1ns / 1ps 2 3 module testbench(input clk); 4 5 wire [31:0]val; 6 wire [7:0]data; 7 8 eth_crc32 crc( 9 .clk(clk), 10 .en(1), 11 .rst(0), 12 .dat(data), 13 .crc(val) 14 ); 15 16 reg [7:0]packet[0:15]; 17 18 reg [7:0]count = 0; 19 20 assign data = packet[count[3:0]]; 21 22 always_ff @(posedge clk) begin 23 $display("crc %x %x",data, val); 24 if (count == 16) begin 25 if (val == 32'hdebb20e3) 26 $display("PASS"); 27 else 28 $display("FAIL"); 29 $finish(); 30 end 31 count <= count + 1; 32 end 33 34 initial begin 35 packet[0] = 8'h6e; 36 packet[1] = 8'hb9; 37 packet[2] = 8'h34; 38 packet[3] = 8'h70; 39 packet[4] = 8'h3b; 40 packet[5] = 8'h77; 41 packet[6] = 8'hc7; 42 packet[7] = 8'hae; 43 packet[8] = 8'h29; 44 packet[9] = 8'h52; 45 packet[10] = 8'h14; 46 packet[11] = 8'h3e; 47 packet[12] = 8'h09; 48 packet[13] = 8'ha6; 49 packet[14] = 8'h94; 50 packet[15] = 8'h60; 51 end 52 53 endmodule 54