eth_mdio_test.sv (1305B)
1 // Copyright 2014 Brian Swetland <swetland@frotz.net> 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 `timescale 1ns / 1ps 16 17 module testbench(input clk); 18 19 reg do_read = 0; 20 reg do_write = 0; 21 reg [31:0]txdata = 32'h80AA0123; 22 wire [15:0]rxdata; 23 wire busy; 24 wire o_dat; 25 wire t_dat; 26 wire o_clk; 27 reg i_raw = 0; 28 wire i_dat = t_dat ? i_raw : o_dat; 29 30 eth_mdio mdio0( 31 .clk(clk), 32 .do_read(do_read), 33 .do_write(do_write), 34 .txdata(txdata), 35 .rxdata(rxdata), 36 .busy(busy), 37 .i_mdio(i_dat), 38 .o_mdio(o_dat), 39 .t_mdio(t_dat), 40 .mdc(o_clk) 41 ); 42 43 integer count = 0; 44 reg next_rd; 45 reg next_wr; 46 47 always_comb begin 48 next_rd = 0; 49 next_wr = 0; 50 if (count == 32768) $finish; 51 if (count == 32) next_rd = 1; 52 end 53 54 always @(posedge clk) begin 55 count <= count + 1; 56 do_read <= next_rd; 57 do_write <= next_wr; 58 end 59 60 endmodule