zynq-sandbox

old FPGA projects for ZYNQ
git clone http://frotz.net/git/zynq-sandbox.git
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eth_packet_gen.sv (1540B)


      1 // Copyright 2014 Brian Swetland <swetland@frotz.net>
      2 //
      3 // Licensed under the Apache License, Version 2.0 (the "License");
      4 // you may not use this file except in compliance with the License.
      5 // You may obtain a copy of the License at
      6 //
      7 //     http://www.apache.org/licenses/LICENSE-2.0
      8 //
      9 // Unless required by applicable law or agreed to in writing, software
     10 // distributed under the License is distributed on an "AS IS" BASIS,
     11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
     12 // See the License for the specific language governing permissions and
     13 // limitations under the License.
     14 
     15 `timescale 1ns / 1ps
     16 
     17 
     18 
     19 module eth_packet_gen(
     20 	input clk50,
     21 	output [1:0]data,
     22 	output packet,
     23 	input start,
     24 	output reg done = 0
     25 	);
     26 
     27 parameter PACKET_COUNT = 5;
     28 parameter PACKET_LENGTH = 145;
     29 
     30 reg [8:0]pcount = PACKET_COUNT;
     31 reg [11:0]plength = PACKET_LENGTH;
     32 reg [11:0]bcount = 0;
     33 reg active = 0;
     34 
     35 reg txpacket = 0;
     36 wire txbusy;
     37 wire txadvance;
     38 
     39 eth_rmii_tx tx0(
     40 	.clk50(clk50),
     41 	.tx(data),
     42 	.txen(packet),
     43 	.data(bcount[7:0]),
     44 	.packet(txpacket),
     45 	.busy(txbusy),
     46 	.advance(txadvance)
     47 	);
     48 
     49 always @(posedge clk50) begin
     50 	if (start) begin
     51 		active <= 1;
     52 	end
     53 	if (txpacket) begin
     54 		if (txadvance) begin
     55 			if (bcount == (PACKET_LENGTH - 1)) begin
     56 				txpacket <= 0;
     57 				bcount <= 0;
     58 			end else begin
     59 				bcount <= bcount + 1;
     60 			end
     61 		end
     62 	end else begin
     63 		if (active && ~txbusy) begin
     64 			if (pcount == 0) begin
     65 				done <= 1;
     66 			end else begin
     67 				pcount <= pcount - 1;
     68 				txpacket <= 1;
     69 			end
     70 		end
     71 	end
     72 end
     73 
     74 endmodule