zynq-sandbox

old FPGA projects for ZYNQ
git clone http://frotz.net/git/zynq-sandbox.git
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eth_rmii_test.sv (2060B)

      1 /* Copyright 2014 Brian Swetland <swetland@frotz.net>
      2  *
      3  * Licensed under the Apache License, Version 2.0 (the "License");
      4  * you may not use this file except in compliance with the License.
      5  * You may obtain a copy of the License at
      6  *
      7  *     http://www.apache.org/licenses/LICENSE-2.0
      8  *
      9  * Unless required by applicable law or agreed to in writing, software
     10  * distributed under the License is distributed on an "AS IS" BASIS,
     11  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
     12  * See the License for the specific language governing permissions and
     13  * limitations under the License.
     14  */
     15 
     16 `timescale 1ns / 1ps
     17 
     18 `ifdef verilator
     19 module testbench(input clk);
     20 `else
     21 module testbench();
     22 reg clk = 0;
     23 always #5 clk = ~clk;
     24 `endif
     25 
     26 // RMII transport between tx and rx
     27 wire [1:0]eth_data;
     28 wire eth_en;
     29 
     30 
     31 wire [7:0]txdata;
     32 reg txpacket = 0;
     33 wire txbusy;
     34 wire txadvance;
     35 
     36 eth_rmii_tx tx(
     37 	.clk50(clk),
     38 	.tx(eth_data),
     39 	.txen(eth_en),
     40 	.data(txdata),
     41 	.packet(txpacket),
     42 	.busy(txbusy),
     43 	.advance(txadvance)
     44 	);
     45 
     46 wire [7:0]rxdata;
     47 wire rxvalid;
     48 wire rxeop;
     49 
     50 eth_rmii_rx rx(
     51 	.clk50(clk),
     52 	.rx(eth_data),
     53 	.crs_dv(eth_en),
     54 	.data(rxdata),
     55 	.valid(rxvalid),
     56 	.eop(rxeop),
     57 	.out_tx(),
     58 	.out_txen()
     59 	);
     60 
     61 reg txgo = 0;
     62 reg wait_eop = 0;
     63 
     64 reg [7:0]pdata[0:15];
     65 reg [3:0]pindex = 0;
     66 
     67 assign txdata = pdata[pindex];
     68 
     69 reg [7:0]start = 8'b10000000;
     70 
     71 always_ff @(posedge clk) begin
     72 	txgo <= start[0];
     73 	start <= { 1'b0, start[7:1] };
     74 end
     75 
     76 
     77 always_ff @(posedge clk) begin
     78 	if (txgo) begin
     79 		txpacket <= 1;
     80 	end
     81 	if (txpacket) begin
     82 		if (txadvance) begin
     83 			if (pindex == 15) begin
     84 				txpacket <= 0;
     85 				wait_eop <= 1;
     86 			end
     87 			pindex <= pindex + 1;
     88 		end
     89 	end
     90 	if (wait_eop & ~txbusy) begin
     91 		$finish;
     92 	end
     93 end
     94 
     95 initial begin
     96 	pdata[0] = 8'hFF;
     97 	pdata[1] = 8'h01;
     98 	pdata[2] = 8'h77;
     99 	pdata[3] = 8'hAA;
    100 	pdata[4] = 8'h00;
    101 	pdata[5] = 8'h10;
    102 	pdata[6] = 8'h20;
    103 	pdata[7] = 8'h30;
    104 	pdata[8] = 8'h40;
    105 	pdata[9] = 8'h50;
    106 	pdata[10] = 8'h60;
    107 	pdata[11] = 8'h70;
    108 	pdata[12] = 8'h80;
    109 	pdata[13] = 8'h90;
    110 	pdata[14] = 8'hAA;
    111 	pdata[15] = 8'h55;
    112 end
    113 	
    114 endmodule