zynq-sandbox

old FPGA projects for ZYNQ
git clone http://frotz.net/git/zynq-sandbox.git
Log | Files | Refs | README

simple_fifo_test.sv (1721B)


      1 // Copyright 2014 Brian Swetland <swetland@frotz.net>
      2 //
      3 // Licensed under the Apache License, Version 2.0 (the "License");
      4 // you may not use this file except in compliance with the License.
      5 // You may obtain a copy of the License at
      6 //
      7 //     http://www.apache.org/licenses/LICENSE-2.0
      8 //
      9 // Unless required by applicable law or agreed to in writing, software
     10 // distributed under the License is distributed on an "AS IS" BASIS,
     11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
     12 // See the License for the specific language governing permissions and
     13 // limitations under the License.
     14 
     15 `timescale 1ns / 1ps
     16 
     17 module testbench(input clk);
     18 
     19 parameter WIDTH = 8;
     20 parameter DEPTH = 4;
     21 
     22 reg wr = 0;
     23 reg rd = 0;
     24 wire rvalid;
     25 wire not_empty;
     26 wire not_full;
     27 
     28 wire [WIDTH-1:0]rdata;
     29 reg  [WIDTH-1:0]wdata = 0;
     30 
     31 simple_fifo #(
     32 	.WIDTH(WIDTH),
     33 	.DEPTH(DEPTH)
     34 	) fifo (
     35 	.clk(clk),
     36 	.rd(rd),
     37 	.wr(wr),
     38 	.rdata(rdata),
     39 	.wdata(wdata),
     40 	.rvalid(rvalid),
     41 	.not_empty(not_empty),
     42 	.not_full(not_full)
     43 	);
     44 
     45 integer count = 0;
     46 
     47 reg next_wr;
     48 reg next_rd;
     49 reg [WIDTH-1:0]next_wdata;
     50 
     51 always_comb begin
     52 	next_wr = 0;
     53 	next_rd = 0;
     54 	next_wdata = wdata;
     55 
     56 	if (count == 10) begin
     57 		next_wr = 1;
     58 		next_wdata = 8'haa;
     59 	end
     60 	if (count == 11) begin
     61 		next_wr = 1;
     62 		next_wdata = 8'hbb;
     63 	end
     64 	if (count == 12) begin
     65 		next_wr = 1;
     66 		next_wdata = 8'hcc;
     67 	end
     68 	if (count == 20) begin
     69 		next_wr = 1;
     70 		next_wdata = 8'h42;
     71 	end
     72 	if (count > 30) begin
     73 		next_wr = 1;
     74 		next_wdata = 8'hee;
     75 	end
     76 
     77 	if ((count > 15) && (count < 25)) next_rd = 1;
     78 	if (count == 50) next_rd = 1;
     79 	if (count == 100) $finish;
     80 end
     81 
     82 always_ff @(posedge clk) begin
     83 	count <= count + 1;
     84 	rd <= next_rd;
     85 	wr <= next_wr;
     86 	wdata <= next_wdata;
     87 end
     88 
     89 endmodule