tmds_encoder.sv (2184B)
1 // Copyright 2014 Brian Swetland <swetland@frotz.net> 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 `timescale 1ns / 1ps 16 17 /* verilator lint_off WIDTH */ 18 module tmds_encoder( 19 input clk, 20 input [7:0]data, 21 input [1:0]ctrl, 22 input active, 23 output reg [9:0]out 24 ); 25 26 reg [3:0]acc = 0; 27 28 wire [8:0]xo; 29 wire [8:0]xn; 30 31 assign xn[0] = data[0]; 32 assign xn[1] = data[1] ~^ xn[0]; 33 assign xn[2] = data[2] ~^ xn[1]; 34 assign xn[3] = data[3] ~^ xn[2]; 35 assign xn[4] = data[4] ~^ xn[3]; 36 assign xn[5] = data[5] ~^ xn[4]; 37 assign xn[6] = data[6] ~^ xn[5]; 38 assign xn[7] = data[7] ~^ xn[6]; 39 assign xn[8] = 0; 40 41 assign xo[0] = data[0]; 42 assign xo[1] = data[1] ^ xo[0]; 43 assign xo[2] = data[2] ^ xo[1]; 44 assign xo[3] = data[3] ^ xo[2]; 45 assign xo[4] = data[4] ^ xo[3]; 46 assign xo[5] = data[5] ^ xo[4]; 47 assign xo[6] = data[6] ^ xo[5]; 48 assign xo[7] = data[7] ^ xo[6]; 49 assign xo[8] = 1; 50 51 wire [3:0]ones = data[0] + data[1] + data[2] + data[3] + data[4] + data[5] + data[6] + data[7]; 52 53 wire use_xn = ((ones > 4) | ((ones == 4) & (data[0] == 0))); 54 55 wire [8:0]tmp = use_xn ? xn : xo; 56 wire [3:0]tmp_ones = tmp[0]+tmp[1]+tmp[2]+tmp[3]+tmp[4]+tmp[5]+tmp[6]+tmp[7]; 57 58 wire no_bias = (acc == 0) | (tmp_ones == 4); 59 60 wire same_sign = (acc[3] == tmp_ones[3]); 61 62 wire inv = no_bias ? (~tmp[8]) : same_sign; 63 64 wire [9:0]enc = { inv, tmp[8], inv ? ~tmp[7:0] : tmp[7:0] }; 65 66 always @(posedge clk) begin 67 if (active) begin 68 out <= enc; 69 acc = acc - 5 + enc[0]+enc[1]+enc[2]+enc[3]+enc[4]+enc[5]+enc[6]+enc[7]+enc[8]+enc[9]; 70 end else begin 71 case (ctrl) 72 2'b00: out <= 10'b1101010100; 73 2'b01: out <= 10'b0010101011; 74 2'b10: out <= 10'b0101010100; 75 2'b11: out <= 10'b1010101011; 76 endcase 77 acc <= 0; 78 end 79 end 80 81 endmodule