uzed_simple_io.xdc (9698B)
1 # ---------------------------------------------------------------------------- 2 # _____ 3 # / \ 4 # /____ \____ 5 # / \===\ \==/ 6 # /___\===\___\/ AVNET Design Resource Center 7 # \======/ www.em.avnet.com/drc 8 # \====/ 9 # ---------------------------------------------------------------------------- 10 # 11 # Created With Avnet UCF Generator V0.4.0 12 # Date: Wednesday, November 27, 2013 13 # Time: 2:10:18 PM 14 # 15 # This design is the property of Avnet. Publication of this 16 # design is not authorized without written consent from Avnet. 17 # 18 # Please direct any questions or issues to the MicroZed Community Forums: 19 # http://www.microzed.org 20 # 21 # Disclaimer: 22 # Avnet, Inc. makes no warranty for the use of this code or design. 23 # This code is provided "As Is". Avnet, Inc assumes no responsibility for 24 # any errors, which may appear in this code, nor does it make a commitment 25 # to update the information contained herein. Avnet, Inc specifically 26 # disclaims any implied warranties of fitness for a particular purpose. 27 # Copyright(c) 2013 Avnet, Inc. 28 # All rights reserved. 29 # 30 # ---------------------------------------------------------------------------- 31 # 32 # Notes: 33 # 34 # 27 November 2013 35 # IO standards based upon Bank 34, Bank 35 Vcco supply options of 1.8V, 36 # 2.5V, or 3.3V are possible based upon the Vadj jumper (J18) settings. 37 # By default, Vadj is expected to be set to 1.8V but if a different 38 # voltage is used for a particular design, then the corresponding IO 39 # standard within this UCF should also be updated to reflect the actual 40 # Vadj jumper selection. 41 # 42 # Net names are not allowed to contain hyphen characters '-' since this 43 # is not a legal VHDL87 or Verilog character within an identifier. 44 # HDL net names are adjusted to contain no hyphen characters '-' but 45 # rather use underscore '_' characters. Comment net name with the hyphen 46 # characters will remain in place since these are intended to match the 47 # schematic net names in order to better enable schematic search. 48 # 49 # In the following, the XDC constraint is matched to the origanal UCF 50 # constraint, UCF commented out above, XDC equivalent placedbelow the UCF. 51 # 52 # ---------------------------------------------------------------------------- 53 54 create_clock -add -name axiclk -period 10.00 -waveform {0 5} [get_nets axiclk] 55 56 # Bank 13, Vcco = Vadj 57 # Set the bank voltage for bank 13. 58 #set_property IOSTANDARD LVCMOS18 [get_ports -filter { IOBANK == 13 } ] 59 60 #set_property PACKAGE_PIN V7 [get_ports {BANK13_LVDS_0_N}] 61 #set_property PACKAGE_PIN U7 [get_ports {BANK13_LVDS_0_P}] 62 #set_property PACKAGE_PIN U10 [get_ports {BANK13_LVDS_1_N}] 63 #set_property PACKAGE_PIN T9 [get_ports {BANK13_LVDS_1_P}] 64 #set_property PACKAGE_PIN W8 [get_ports {BANK13_LVDS_2_N}] 65 #set_property PACKAGE_PIN V8 [get_ports {BANK13_LVDS_2_P}] 66 #set_property PACKAGE_PIN U5 [get_ports {BANK13_LVDS_3_N}] 67 #set_property PACKAGE_PIN T5 [get_ports {BANK13_LVDS_3_P}] 68 #set_property PACKAGE_PIN Y13 [get_ports {BANK13_LVDS_4_N}] 69 #set_property PACKAGE_PIN Y12 [get_ports {BANK13_LVDS_4_P}] 70 #set_property PACKAGE_PIN V10 [get_ports {BANK13_LVDS_5_N}] 71 #set_property PACKAGE_PIN V11 [get_ports {BANK13_LVDS_5_P}] 72 #set_property PACKAGE_PIN W6 [get_ports {BANK13_LVDS_6_N}] 73 #set_property PACKAGE_PIN V6 [get_ports {BANK13_LVDS_6_P}] 74 #set_property PACKAGE_PIN V5 [get_ports {BANK13_SE_0}] 75 76 # Bank 34, Vcco = Vadj 77 # Set the bank voltage for bank 34. 78 #set_property IOSTANDARD LVCMOS18 [get_ports -filter { IOBANK == 34 } ] 79 80 #set_property PACKAGE_PIN T10 [get_ports {JX1_LVDS_0_N}] 81 #set_property PACKAGE_PIN T11 [get_ports {JX1_LVDS_0_P}] 82 #set_property PACKAGE_PIN U12 [get_ports {JX1_LVDS_1_N}] 83 #set_property PACKAGE_PIN T12 [get_ports {JX1_LVDS_1_P}] 84 #set_property PACKAGE_PIN U15 [get_ports {X1_LVDS_10_N}] 85 #set_property PACKAGE_PIN U14 [get_ports {JX1_LVDS_10_P}] 86 #set_property PACKAGE_PIN U19 [get_ports {JX1_LVDS_11_N}] 87 #set_property PACKAGE_PIN U18 [get_ports {JX1_LVDS_11_P}] 88 #set_property PACKAGE_PIN P19 [get_ports {JX1_LVDS_12_N}] 89 #set_property PACKAGE_PIN N18 [get_ports {JX1_LVDS_12_P}] 90 #set_property PACKAGE_PIN P20 [get_ports {JX1_LVDS_13_N}] 91 #set_property PACKAGE_PIN N20 [get_ports {JX1_LVDS_13_P}] 92 #set_property PACKAGE_PIN U20 [get_ports {JX1_LVDS_14_N}] 93 #set_property PACKAGE_PIN T20 [get_ports {JX1_LVDS_14_P}] 94 #set_property PACKAGE_PIN W20 [get_ports {JX1_LVDS_15_N}] 95 #set_property PACKAGE_PIN V20 [get_ports {JX1_LVDS_15_P}] 96 #set_property PACKAGE_PIN Y19 [get_ports {JX1_LVDS_16_N}] 97 #set_property PACKAGE_PIN Y18 [get_ports {JX1_LVDS_16_P}] 98 #set_property PACKAGE_PIN W16 [get_ports {JX1_LVDS_17_N}] 99 #set_property PACKAGE_PIN V16 [get_ports {JX1_LVDS_17_P}] 100 #set_property PACKAGE_PIN R17 [get_ports {JX1_LVDS_18_N}] 101 #set_property PACKAGE_PIN R16 [get_ports {JX1_LVDS_18_P}] 102 #set_property PACKAGE_PIN R18 [get_ports {JX1_LVDS_19_N}] 103 #set_property PACKAGE_PIN T17 [get_ports {JX1_LVDS_19_P}] 104 #set_property PACKAGE_PIN V13 [get_ports {JX1_LVDS_2_N}] 105 #set_property PACKAGE_PIN U13 [get_ports {JX1_LVDS_2_P}] 106 #set_property PACKAGE_PIN V18 [get_ports {JX1_LVDS_20_N}] 107 #set_property PACKAGE_PIN V17 [get_ports {JX1_LVDS_20_P}] 108 #set_property PACKAGE_PIN W19 [get_ports {JX1_LVDS_21_N}] 109 #set_property PACKAGE_PIN W18 [get_ports {JX1_LVDS_21_P}] 110 #set_property PACKAGE_PIN P18 [get_ports {JX1_LVDS_22_N}] 111 #set_property PACKAGE_PIN N17 [get_ports {JX1_LVDS_22_P}] 112 #set_property PACKAGE_PIN P16 [get_ports {JX1_LVDS_23_N}] 113 #set_property PACKAGE_PIN P15 [get_ports {JX1_LVDS_23_P}] 114 #set_property PACKAGE_PIN W13 [get_ports {JX1_LVDS_3_N}] 115 #set_property PACKAGE_PIN V12 [get_ports {JX1_LVDS_3_P}] 116 #set_property PACKAGE_PIN T15 [get_ports {JX1_LVDS_4_N}] 117 #set_property PACKAGE_PIN T14 [get_ports {JX1_LVDS_4_P}] 118 #set_property PACKAGE_PIN R14 [get_ports {JX1_LVDS_5_N}] 119 #set_property PACKAGE_PIN P14 [get_ports {JX1_LVDS_5_P}] 120 #set_property PACKAGE_PIN Y17 [get_ports {JX1_LVDS_6_N}] 121 #set_property PACKAGE_PIN Y16 [get_ports {JX1_LVDS_6_P}] 122 #set_property PACKAGE_PIN Y14 [get_ports {JX1_LVDS_7_N}] 123 #set_property PACKAGE_PIN W14 [get_ports {JX1_LVDS_7_P}] 124 #set_property PACKAGE_PIN U17 [get_ports {JX1_LVDS_8_N}] 125 #set_property PACKAGE_PIN T16 [get_ports {JX1_LVDS_8_P}] 126 #set_property PACKAGE_PIN W15 [get_ports {JX1_LVDS_9_N}] 127 #set_property PACKAGE_PIN V15 [get_ports {JX1_LVDS_9_P}] 128 #set_property PACKAGE_PIN R19 [get_ports {JX1_SE_0}] 129 #set_property PACKAGE_PIN T19 [get_ports {JX1_SE_1}] 130 131 # Bank 35, Vcco = Vadj 132 # Set the bank voltage for bank 35. 133 #set_property IOSTANDARD LVCMOS18 [get_ports -filter { IOBANK == 35 } ] 134 135 #set_property PACKAGE_PIN B20 [get_ports {JX2_LVDS_0_N}] 136 #set_property PACKAGE_PIN C20 [get_ports {JX2_LVDS_0_P}] 137 #set_property PACKAGE_PIN A20 [get_ports {JX2_LVDS_1_N}] 138 #set_property PACKAGE_PIN B19 [get_ports {JX2_LVDS_1_P}] 139 #set_property PACKAGE_PIN L17 [get_ports {JX2_LVDS_10_N}] 140 #set_property PACKAGE_PIN L16 [get_ports {JX2_LVDS_10_P}] 141 #set_property PACKAGE_PIN K18 [get_ports {JX2_LVDS_11_N}] 142 #set_property PACKAGE_PIN K17 [get_ports {JX2_LVDS_11_P}] 143 #set_property PACKAGE_PIN H17 [get_ports {JX2_LVDS_12_N}] 144 #set_property PACKAGE_PIN H16 [get_ports {JX2_LVDS_12_P}] 145 #set_property PACKAGE_PIN H18 [get_ports {JX2_LVDS_13_N}] 146 #set_property PACKAGE_PIN J18 [get_ports {JX2_LVDS_13_P}] 147 #set_property PACKAGE_PIN G18 [get_ports {JX2_LVDS_14_N}] 148 #set_property PACKAGE_PIN G17 [get_ports {JX2_LVDS_14_P}] 149 #set_property PACKAGE_PIN F20 [get_ports {JX2_LVDS_15_N}] 150 #set_property PACKAGE_PIN F19 [get_ports {JX2_LVDS_15_P}] 151 #set_property PACKAGE_PIN G20 [get_ports {JX2_LVDS_16_N}] 152 #set_property PACKAGE_PIN G19 [get_ports {JX2_LVDS_16_P}] 153 #set_property PACKAGE_PIN H20 [get_ports {JX2_LVDS_17_N}] 154 #set_property PACKAGE_PIN J20 [get_ports {JX2_LVDS_17_P}] 155 #set_property PACKAGE_PIN J14 [get_ports {JX2_LVDS_18_N}] 156 #set_property PACKAGE_PIN K14 [get_ports {JX2_LVDS_18_P}] 157 #set_property PACKAGE_PIN G15 [get_ports {JX2_LVDS_19_N}] 158 #set_property PACKAGE_PIN H15 [get_ports {JX2_LVDS_19_P}] 159 #set_property PACKAGE_PIN D18 [get_ports {JX2_LVDS_2_N}] 160 #set_property PACKAGE_PIN E17 [get_ports {JX2_LVDS_2_P}] 161 #set_property PACKAGE_PIN N16 [get_ports {JX2_LVDS_20_N}] 162 #set_property PACKAGE_PIN N15 [get_ports {JX2_LVDS_20_P}] 163 #set_property PACKAGE_PIN L15 [get_ports {JX2_LVDS_21_N}] 164 #set_property PACKAGE_PIN L14 [get_ports {JX2_LVDS_21_P}] 165 #set_property PACKAGE_PIN M15 [get_ports {JX2_LVDS_22_N}] 166 #set_property PACKAGE_PIN M14 [get_ports {JX2_LVDS_22_P}] 167 #set_property PACKAGE_PIN J16 [get_ports {JX2_LVDS_23_N}] 168 #set_property PACKAGE_PIN K16 [get_ports {JX2_LVDS_23_P}] 169 #set_property PACKAGE_PIN D20 [get_ports {JX2_LVDS_3_N}] 170 #set_property PACKAGE_PIN D19 [get_ports {JX2_LVDS_3_P}] 171 #set_property PACKAGE_PIN E19 [get_ports {JX2_LVDS_4_N}] 172 #set_property PACKAGE_PIN E18 [get_ports {JX2_LVDS_4_P}] 173 #set_property PACKAGE_PIN F17 [get_ports {JX2_LVDS_5_N}] 174 #set_property PACKAGE_PIN F16 [get_ports {JX2_LVDS_5_P}] 175 #set_property PACKAGE_PIN L20 [get_ports {JX2_LVDS_6_N}] 176 #set_property PACKAGE_PIN L19 [get_ports {JX2_LVDS_6_P}] 177 #set_property PACKAGE_PIN M20 [get_ports {JX2_LVDS_7_N}] 178 #set_property PACKAGE_PIN M19 [get_ports {JX2_LVDS_7_P}] 179 #set_property PACKAGE_PIN M18 [get_ports {JX2_LVDS_8_N}] 180 #set_property PACKAGE_PIN M17 [get_ports {JX2_LVDS_8_P}] 181 #set_property PACKAGE_PIN J19 [get_ports {JX2_LVDS_9_N}] 182 #set_property PACKAGE_PIN K19 [get_ports {JX2_LVDS_9_P}] 183 #set_property PACKAGE_PIN G14 [get_ports {JX2_SE_0}] 184 #set_property PACKAGE_PIN J15 [get_ports {JX2_SE_1}]