zybo-axi-test.sv (4268B)
1 // Copyright 2014 Brian Swetland <swetland@frotz.net> 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 `timescale 1ns / 1ps 16 17 // MEM2MEM causes ch0 reader to send to ch1 writer 18 //`define MEM2MEM 19 20 module top(); 21 22 wire clk; 23 24 axi_ifc #(.IWIDTH(12),.AXI3(1)) axi_ctl(); 25 axi_ifc #(.IWIDTH(6),.DWIDTH(64),.AXI3(1)) axi_dma0(); 26 axi_ifc #(.IWIDTH(6),.DWIDTH(64),.AXI3(1)) axi_dma1(); 27 axi_ifc #(.IWIDTH(6),.DWIDTH(64),.AXI3(1)) axi_dma2(); 28 axi_ifc #(.IWIDTH(6),.DWIDTH(64),.AXI3(1)) axi_dma3(); 29 30 reg_ifc #(.AWIDTH(3)) ri(); 31 32 axi_registers regs0( 33 .clk(clk), 34 .s(axi_ctl), 35 .rm(ri) 36 ); 37 38 zynq_ps7 zynq( 39 .fclk0(clk), 40 .s_axi_hp0_clk(clk), 41 .s_axi_hp0(axi_dma0), 42 .s_axi_hp1_clk(clk), 43 .s_axi_hp1(axi_dma1), 44 .s_axi_hp2_clk(clk), 45 .s_axi_hp2(axi_dma2), 46 .s_axi_hp3_clk(clk), 47 .s_axi_hp3(axi_dma3), 48 .m_axi_gp0_clk(clk), 49 .m_axi_gp0(axi_ctl) 50 ); 51 52 wire [31:0]rcc0; 53 wire [31:0]rcc1; 54 wire [31:0]rcc2; 55 wire [31:0]rcc3; 56 57 `ifdef MEM2MEM 58 wxire [63:0]r0_data; 59 wire r0_valid; 60 wire r0_ready; 61 `endif 62 63 axi_hp_dma_reader #(.DWIDTH(64)) dma_r0( 64 .clk(clk), 65 .m(axi_dma0.reader), 66 .txn_addr(32'h02000000), 67 .txn_count(262144), 68 .txn_start(ri.wr & ri.wdata[4]), 69 .txn_busy(), 70 `ifdef MEM2MEM 71 .data(r0_data), 72 .valid(r0_valid), 73 .ready(r0_ready), 74 `else 75 .data(), 76 .valid(), 77 .ready(1), 78 `endif 79 .cyc_count(rcc0) 80 ); 81 82 axi_hp_dma_reader #(.DWIDTH(64)) dma_r1( 83 .clk(clk), 84 .m(axi_dma1.reader), 85 .txn_addr(32'h02100000), 86 .txn_count(262144), 87 .txn_start(ri.wr & ri.wdata[5]), 88 .txn_busy(), 89 .data(), 90 .valid(), 91 .ready(1), 92 .cyc_count(rcc1) 93 ); 94 95 axi_hp_dma_reader #(.DWIDTH(64)) dma_r2( 96 .clk(clk), 97 .m(axi_dma2.reader), 98 .txn_addr(32'h02200000), 99 .txn_count(262144), 100 .txn_start(ri.wr & ri.wdata[6]), 101 .txn_busy(), 102 .data(), 103 .valid(), 104 .ready(1), 105 .cyc_count(rcc2) 106 ); 107 108 axi_hp_dma_reader #(.DWIDTH(64)) dma_r3( 109 .clk(clk), 110 .m(axi_dma3.reader), 111 .txn_addr(32'h02300000), 112 .txn_count(262144), 113 .txn_start(ri.wr & ri.wdata[7]), 114 .txn_busy(), 115 .data(), 116 .valid(), 117 .ready(1), 118 .cyc_count(rcc3) 119 ); 120 121 wire [31:0]cc0; 122 wire rdy0; 123 reg [31:0]count0 = 0; 124 always @(posedge clk) 125 if (rdy0) count0 <= count0 + 1; 126 127 axi_hp_dma_writer #(.DWIDTH(64)) dma_w0( 128 .clk(clk), 129 .m(axi_dma0.writer), 130 .txn_addr(32'h01000000), 131 .txn_count(262144), 132 .txn_start(ri.wr & ri.wdata[0]), 133 .txn_busy(), 134 .data({ 32'h00bbccdd, count0 }), 135 .valid(1), 136 .ready(rdy0), 137 .cyc_count(cc0) 138 ); 139 140 wire [31:0]cc1; 141 wire rdy1; 142 reg [31:0]count1 = 0; 143 always @(posedge clk) 144 if (rdy1) count1 <= count1 + 1; 145 146 axi_hp_dma_writer #(.DWIDTH(64)) dma_w1( 147 .clk(clk), 148 .m(axi_dma1.writer), 149 .txn_addr(32'h01100000), 150 .txn_count(262144), 151 .txn_start(ri.wr & ri.wdata[1]), 152 .txn_busy(), 153 `ifdef MEM2MEM 154 .data(r0_data), 155 .valid(r0_valid), 156 .ready(r0_ready), 157 `else 158 .data({ 32'h11bbccdd, count1 }), 159 .valid(1), 160 .ready(rdy1), 161 `endif 162 .cyc_count(cc1) 163 ); 164 165 wire [31:0]cc2; 166 wire rdy2; 167 reg [31:0]count2 = 0; 168 always @(posedge clk) 169 if (rdy2) count2 <= count2 + 1; 170 171 axi_hp_dma_writer #(.DWIDTH(64)) dma_w2( 172 .clk(clk), 173 .m(axi_dma2.writer), 174 .txn_addr(32'h01200000), 175 .txn_count(262144), 176 .txn_start(ri.wr & ri.wdata[2]), 177 .txn_busy(), 178 .data({ 32'h22bbccdd, count2 }), 179 .valid(1), 180 .ready(rdy2), 181 .cyc_count(cc2) 182 ); 183 184 wire [31:0]cc3; 185 wire rdy3; 186 reg [31:0]count3 = 0; 187 always @(posedge clk) 188 if (rdy3) count3 <= count3 + 1; 189 190 axi_hp_dma_writer #(.DWIDTH(64)) dma_w3( 191 .clk(clk), 192 .m(axi_dma3.writer), 193 .txn_addr(32'h01300000), 194 .txn_count(262144), 195 .txn_start(ri.wr & ri.wdata[3]), 196 .txn_busy(), 197 .data({ 32'h33bbccdd, count3 }), 198 .valid(1), 199 .ready(rdy3), 200 .cyc_count(cc3) 201 ); 202 203 always @(posedge clk) 204 if (ri.rd) case (ri.raddr) 205 0: ri.rdata <= cc0; 206 1: ri.rdata <= cc1; 207 2: ri.rdata <= cc2; 208 3: ri.rdata <= cc3; 209 4: ri.rdata <= rcc0; 210 5: ri.rdata <= rcc1; 211 6: ri.rdata <= rcc2; 212 7: ri.rdata <= rcc3; 213 //default: ri.rdata <= 32'ha7a7a7a7; 214 endcase 215 216 endmodule 217