zybo_adc.sv (1814B)
1 // Copyright 2014 Travis Geiselbrecht <geist@foobox.com> 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 `timescale 1ns / 1ps 16 17 module top( 18 input clk, 19 input [3:0]sw, 20 input [3:0]btn, 21 input [3:0]ja_p, 22 input [3:0]ja_n, 23 output [3:0]jb_p, 24 output [3:0]jb_n, 25 output reg [3:0]led 26 ); 27 28 axi_ifc #(.IWIDTH(12),.AXI3(1)) axi_ctl(); 29 30 wire fclk; 31 wire axiclk = clk; // 125Mhz clock from external ethernet phy 32 33 zynq_ps7 zynq( 34 .fclk0(fclk), 35 .m_axi_gp0_clk(axiclk), 36 .m_axi_gp0(axi_ctl) 37 ); 38 39 wire vn = 0; 40 wire vp = 0; 41 wire [15:0] aux_channel_n; 42 wire [15:0] aux_channel_p; 43 44 assign aux_channel_n[14] = ja_n[0]; 45 assign aux_channel_p[14] = ja_p[0]; 46 assign aux_channel_n[7] = ja_n[1]; 47 assign aux_channel_p[7] = ja_p[1]; 48 assign aux_channel_n[15] = ja_n[2]; 49 assign aux_channel_p[15] = ja_p[2]; 50 assign aux_channel_n[6] = ja_n[3]; 51 assign aux_channel_p[6] = ja_p[3]; 52 53 wire [3:0] adc_debug_out; 54 55 xadc #( 56 .CLKDIV(5) 57 ) 58 adc( 59 .clk(axiclk), 60 .rst(btn[0]), 61 62 .vn(vn), 63 .vp(vp), 64 .aux_channel_n(aux_channel_n), 65 .aux_channel_p(aux_channel_p), 66 67 .debug_out(adc_debug_out), 68 69 .axi(axi_ctl) 70 ); 71 72 assign jb_p = adc_debug_out; 73 74 /* 75 // debugging 76 assign led[0] = adc_eoc; 77 assign led[1] = adc_eos; 78 assign led[2] = adc_busy; 79 80 assign jb_p[0] = adc_eoc; 81 assign jb_p[1] = adc_eos; 82 assign jb_p[2] = rd; 83 */ 84 85 endmodule 86 87 // vim: set noexpandtab: