zybo_eth.sv (3490B)
1 // Copyright 2014 Brian Swetland <swetland@frotz.net> 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 `timescale 1ns / 1ps 16 17 module top( 18 input clk, 19 output [3:0]led, 20 21 output phy0_mdc, 22 //output phy0_mdio, 23 output phy0_clk, 24 output phy0_txen, 25 output [1:0]phy0_tx, 26 input phy0_crs, 27 input [1:0]phy0_rx 28 ); 29 30 assign led = 0; 31 32 wire clk50; 33 34 mmcm_1in_3out #( 35 .CLKIN_PERIOD(8.0), 36 .VCO_MUL(8.000), 37 .VCO_DIV(1), 38 .OUT0_DIV(20.000), 39 .OUT1_DIV(10), 40 .OUT2_DIV(10) 41 ) mmcm0 ( 42 .i_clk(clk), 43 .o_clk0(clk50), 44 .o_clk1(), 45 .o_clk2() 46 ); 47 48 assign phy0_clk = clk50; 49 assign phy0_mdc = 1; 50 51 wire [7:0]rxdata; 52 wire rxvalid; 53 wire rxeop; 54 55 (* keep_hierarchy = "yes" *) 56 eth_rmii_rx phy0rx( 57 .clk50(clk50), 58 .rx(phy0_rx), 59 .crs_dv(phy0_crs), 60 .data(rxdata), 61 .valid(rxvalid), 62 .eop(rxeop), 63 .sop(), 64 .out_tx(), 65 .out_txen() 66 ); 67 68 wire go; 69 70 reg [7:0]txptr = 0; 71 reg [7:0]pdata[0:63]; 72 initial $readmemh("testpacket.hex", pdata); 73 74 wire txbusy; 75 wire txadvance; 76 wire [7:0]txdata = pdata[txptr[5:0]]; 77 reg txpacket = 0; 78 79 always @(posedge clk50) begin 80 if (txpacket) begin 81 if (txadvance) begin 82 txptr <= txptr + 1; 83 if (txptr == 63) begin 84 txpacket <= 0; 85 txptr <= 0; 86 end 87 end 88 end else if (go) begin 89 txpacket <= 1; 90 end 91 end 92 93 eth_rmii_tx phy0tx( 94 .clk50(clk50), 95 .tx(phy0_tx), 96 .txen(phy0_txen), 97 .data(txdata), 98 .packet(txpacket), 99 .busy(txbusy), 100 .advance(txadvance) 101 ); 102 103 (* keep_hierarchy = "yes" *) 104 packetlogger log0( 105 .clk50(clk50), 106 .rxdata(rxdata), 107 .rxvalid(rxvalid), 108 .rxeop(rxeop), 109 .go(go) 110 ); 111 112 endmodule 113 114 module packetlogger( 115 input clk50, 116 input [7:0]rxdata, 117 input rxvalid, 118 input rxeop, 119 output reg go = 0 120 ); 121 122 reg [11:0]rdptr = 0; 123 reg [11:0]rxptr = 0; 124 reg [11:0]next_rdptr; 125 reg [11:0]next_rxptr; 126 127 wire [8:0]rdata; 128 reg bufrd = 0; 129 130 ram rxbuffer( 131 .clk(clk50), 132 .wen(rxvalid | rxeop), 133 .waddr(rxptr), 134 .wdata( { rxeop, rxdata } ), 135 .ren(bufrd), 136 .raddr(rdptr), 137 .rdata(rdata) 138 ); 139 140 wire [31:0]dbg_wdata; 141 reg [31:0]dbg_rdata; 142 wire [2:0]dbg_addr; 143 wire dbg_rd; 144 wire dbg_wr; 145 146 always_comb begin 147 next_rxptr = rxptr; 148 next_rdptr = rdptr; 149 bufrd = 0; 150 if (rxvalid | rxeop) begin 151 if (rxptr != 12'hFFF) 152 next_rxptr = rxptr + 1; 153 end 154 if (dbg_rd) begin 155 if (dbg_addr == 1) begin 156 next_rdptr = rdptr + 1; 157 bufrd = 1; 158 end 159 end 160 case (dbg_addr) 161 0: dbg_rdata = 32'h12345678; 162 1: dbg_rdata = { 23'd0, rdata }; 163 2: dbg_rdata = { 20'd0, rxptr }; 164 default: dbg_rdata = 0; 165 endcase 166 end 167 168 always_ff @(posedge clk50) begin 169 rxptr <= next_rxptr; 170 rdptr <= next_rdptr; 171 if (dbg_wr) begin 172 go <= 1; 173 end else begin 174 go <= 0; 175 end 176 end 177 178 (* keep_hierarchy = "yes" *) 179 jtag_debug_port port0( 180 .clk(clk50), 181 .o_wdata(dbg_wdata), 182 .i_rdata(dbg_rdata), 183 .o_addr(dbg_addr), 184 .o_rd(dbg_rd), 185 .o_wr(dbg_wr) 186 ); 187 188 endmodule 189 190 module ram( 191 input clk, 192 input ren, 193 input [11:0]raddr, 194 output reg [8:0]rdata, 195 input wen, 196 input [11:0]waddr, 197 input [8:0]wdata 198 ); 199 200 reg [8:0]memory[0:4095]; 201 202 always_ff @(posedge clk) begin 203 if (ren) 204 rdata <= memory[raddr]; 205 if (wen) 206 memory[waddr] <= wdata; 207 end 208 209 endmodule 210