zybo_eth.xdc (3455B)
1 2 ##Clock signal 3 ##IO_L11P_T1_SRCC_35 4 set_property PACKAGE_PIN L16 [get_ports clk] 5 set_property IOSTANDARD LVCMOS33 [get_ports clk] 6 create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports clk] 7 8 # 30 MHz JTAG TCK 9 create_clock -period 33.333 -name jtag_tck [get_pins log0/port0/bscan/TCK] 10 11 # human readable generated clock name 12 create_generated_clock -name clk50 [get_pins mmcm0/mmcm_adv_inst/CLKOUT0] 13 14 set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks sys_clk_pin] -group jtag_tck 15 16 ##LEDs 17 ##IO_L23P_T3_35 18 set_property PACKAGE_PIN M14 [get_ports {led[0]}] 19 set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}] 20 21 ##IO_L23N_T3_35 22 set_property PACKAGE_PIN M15 [get_ports {led[1]}] 23 set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}] 24 25 ##IO_0_35 26 set_property PACKAGE_PIN G14 [get_ports {led[2]}] 27 set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}] 28 29 ##IO_L3N_T0_DQS_AD1N_35 30 set_property PACKAGE_PIN D18 [get_ports {led[3]}] 31 set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}] 32 33 ##Pmod Header JB 34 ##IO_L15N_T2_DQS_34 35 set_property PACKAGE_PIN U20 [get_ports {phy0_rx[1]}] 36 set_property IOSTANDARD LVCMOS33 [get_ports {phy0_rx[1]}] 37 38 ##IO_L15P_T2_DQS_34 39 set_property PACKAGE_PIN T20 [get_ports {phy0_tx[0]}] 40 set_property IOSTANDARD LVCMOS33 [get_ports {phy0_tx[0]}] 41 set_property SLEW FAST [get_ports {phy0_tx[0]}] 42 43 ##IO_L16N_T2_34 44 set_property PACKAGE_PIN W20 [get_ports {phy0_mdc}] 45 set_property IOSTANDARD LVCMOS33 [get_ports {phy0_mdc}] 46 47 ##IO_L16P_T2_34 48 set_property PACKAGE_PIN V20 [get_ports {phy0_crs}] 49 set_property IOSTANDARD LVCMOS33 [get_ports {phy0_crs}] 50 51 ##IO_L17N_T2_34 52 set_property PACKAGE_PIN Y19 [get_ports {phy0_rx[0]}] 53 set_property IOSTANDARD LVCMOS33 [get_ports {phy0_rx[0]}] 54 55 ##IO_L17P_T2_34 56 set_property PACKAGE_PIN Y18 [get_ports {phy0_txen}] 57 set_property IOSTANDARD LVCMOS33 [get_ports {phy0_txen}] 58 set_property SLEW FAST [get_ports {phy0_txen}] 59 60 ##IO_L22N_T3_34 61 set_property PACKAGE_PIN W19 [get_ports {phy0_tx[1]}] 62 set_property IOSTANDARD LVCMOS33 [get_ports {phy0_tx[1]}] 63 set_property SLEW FAST [get_ports {phy0_tx[1]}] 64 65 ##IO_L22P_T3_34 66 set_property PACKAGE_PIN W18 [get_ports {phy0_clk}] 67 set_property IOSTANDARD LVCMOS33 [get_ports {phy0_clk}] 68 set_property SLEW FAST [get_ports {phy0_clk}] 69 set_property DRIVE 8 [get_ports {phy0_clk}] 70 71 ##Pmod Header JD 72 ##IO_L5N_T0_34 73 #set_property PACKAGE_PIN T15 [get_ports {phy1_rx1}] 74 #set_property IOSTANDARD LVCMOS33 [get_ports {phy1_rx1}] 75 76 ##IO_L5P_T0_34 77 #set_property PACKAGE_PIN T14 [get_ports {phy1_tx0}] 78 #set_property IOSTANDARD LVCMOS33 [get_ports {phy1_tx0}] 79 80 ##IO_L6N_T0_VREF_34 81 #set_property PACKAGE_PIN R14 [get_ports {phy1_mdc}] 82 #set_property IOSTANDARD LVCMOS33 [get_ports {phy1_mdc}] 83 84 ##IO_L6P_T0_34 85 #set_property PACKAGE_PIN P14 [get_ports {phy1_crs}] 86 #set_property IOSTANDARD LVCMOS33 [get_ports {phy1_crs}] 87 88 ##IO_L11N_T1_SRCC_34 89 #set_property PACKAGE_PIN U15 [get_ports {phy1_rx0}] 90 #set_property IOSTANDARD LVCMOS33 [get_ports {phy1_rx0}] 91 92 ##IO_L11P_T1_SRCC_34 93 #set_property PACKAGE_PIN U14 [get_ports {phy1_txen}] 94 #set_property IOSTANDARD LVCMOS33 [get_ports {phy1_txen}] 95 96 ##IO_L21N_T3_DQS_34 97 #set_property PACKAGE_PIN V18 [get_ports {phy1_mdio}] 98 #set_property IOSTANDARD LVCMOS33 [get_ports {phy1_mdio}] 99 100 ##IO_L21P_T3_DQS_34 101 #set_property PACKAGE_PIN V17 [get_ports {phy1_clk}] 102 #set_property IOSTANDARD LVCMOS33 [get_ports {phy1_clk}] 103