zynq-sandbox

old FPGA projects for ZYNQ
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zybo_eth_capture.sv (3113B)

      1 // Copyright 2014 Brian Swetland <swetland@frotz.net>
      2 //
      3 // Licensed under the Apache License, Version 2.0 (the "License");
      4 // you may not use this file except in compliance with the License.
      5 // You may obtain a copy of the License at
      6 //
      7 //     http://www.apache.org/licenses/LICENSE-2.0
      8 //
      9 // Unless required by applicable law or agreed to in writing, software
     10 // distributed under the License is distributed on an "AS IS" BASIS,
     11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
     12 // See the License for the specific language governing permissions and
     13 // limitations under the License.
     14 
     15 `timescale 1ns / 1ps
     16 
     17 module top(
     18 	input clk,
     19 	output [3:0]led,
     20 
     21 	output phy0_mdc,
     22 	output phy0_clk,
     23 	output phy0_txen,
     24 	output [1:0]phy0_tx,
     25 	input phy0_crs,
     26 	input [1:0]phy0_rx,
     27 
     28 	output phy1_mdc,
     29 	output phy1_clk,
     30 	output phy1_txen,
     31 	output [1:0]phy1_tx,
     32 	input phy1_crs,
     33 	input [1:0]phy1_rx
     34 	);
     35 
     36 assign led = 0;
     37 
     38 wire clk50;
     39 
     40 mmcm_1in_3out #(
     41 	.CLKIN_PERIOD(8.0),
     42 	.VCO_MUL(8.000),
     43 	.VCO_DIV(1),
     44 	.OUT0_DIV(20.000),
     45 	.OUT1_DIV(10),
     46 	.OUT2_DIV(10)
     47 	) mmcm0 (
     48 	.i_clk(clk),
     49 	.o_clk0(clk50),
     50 	.o_clk1(),
     51 	.o_clk2()
     52 	);
     53 
     54 assign phy0_clk = clk50;
     55 assign phy0_mdc = 1;
     56 assign phy1_clk = clk50;
     57 assign phy1_mdc = 1;
     58 
     59 wire [7:0]rx0data;
     60 wire rx0valid;
     61 wire rx0eop;
     62 wire rx0sop;
     63 
     64 (* keep_hierarchy = "yes" *)
     65 eth_rmii_rx phy0rx(
     66 	.clk50(clk50),
     67 	.rx(phy0_rx),
     68 	.crs_dv(phy0_crs),
     69 	.data(rx0data),
     70 	.valid(rx0valid),
     71 	.eop(rx0eop),
     72 	.sop(rx0sop),
     73 	.out_tx(phy1_tx),
     74 	.out_txen(phy1_txen)
     75 	);
     76 
     77 wire [7:0]rx1data;
     78 wire rx1valid;
     79 wire rx1eop;
     80 wire rx1sop;
     81 
     82 (* keep_hierarchy = "yes" *)
     83 eth_rmii_rx phy1rx(
     84 	.clk50(clk50),
     85 	.rx(phy1_rx),
     86 	.crs_dv(phy1_crs),
     87 	.data(rx1data),
     88 	.valid(rx1valid),
     89 	.eop(rx1eop),
     90 	.sop(rx1sop),
     91 	.out_tx(phy0_tx),
     92 	.out_txen(phy0_txen)
     93 	);
     94 
     95 axi_ifc #(.IWIDTH(12),.AXI3(1)) axi_ctl();
     96 axi_ifc #(.IWIDTH(6),.AXI3(1)) axi_dma0();
     97 axi_ifc #(.IWIDTH(6),.AXI3(1)) axi_dma1();
     98 
     99 zynq_ps7 zynq(
    100 	.fclk0(),
    101 	.m_axi_gp0_clk(clk),
    102 	.m_axi_gp0(axi_ctl),
    103 	.s_axi_gp0_clk(clk),
    104 	.s_axi_gp0(axi_dma0),
    105 	.s_axi_gp1_clk(clk),
    106 	.s_axi_gp1(axi_dma1)
    107 	);
    108 
    109 reg cap_enable = 0;
    110 reg cap_reset = 0;
    111 
    112 (* keep_hierarchy = "yes" *)
    113 eth_capture #(
    114 	.BASE_ADDR(32'h10000000)
    115 	) cap0 (
    116 	.clk50(clk50),
    117 	.rxsop(rx0sop),
    118 	.rxeop(rx0eop),
    119 	.rxdata(rx0data),
    120 	.rxvalid(rx0valid),
    121 	.clk(clk),
    122 	.reset(cap_reset),
    123 	.enable(cap_enable),
    124 	.axi_dma(axi_dma0)
    125 	);
    126 
    127 (* keep_hierarchy = "yes" *)
    128 eth_capture #(
    129 	.BASE_ADDR(32'h10400000)
    130 	) cap1 (
    131 	.clk50(clk50),
    132 	.rxsop(rx1sop),
    133 	.rxeop(rx1eop),
    134 	.rxdata(rx1data),
    135 	.rxvalid(rx1valid),
    136 	.clk(clk),
    137 	.reset(cap_reset),
    138 	.enable(cap_enable),
    139 	.axi_dma(axi_dma1)
    140 	);
    141 
    142 wire wr;
    143 wire [31:0]wdata;
    144 
    145 wire rrd;
    146 wire [1:0]rreg;
    147 reg [31:0]rdata = 0;
    148 
    149 always_ff @(posedge clk) begin
    150 	if (rrd) case(rreg)
    151 		0: rdata <= 32'haabbccdd;
    152 		1: rdata <= 0;
    153 		2: rdata <= 0;
    154 		3: rdata <= 0;
    155 	endcase
    156 end
    157 
    158 axi_registers regs(
    159 	.clk(clk),
    160 	.s(axi_ctl),
    161 	.o_rreg(rreg),
    162 	.o_wreg(),
    163 	.i_rdata(rdata),
    164 	.o_wdata(wdata),
    165 	.o_rd(rrd),
    166 	.o_wr(wr)
    167 	);
    168 
    169 always @(posedge clk) begin
    170 	if (wr) begin
    171 		cap_enable <= wdata[0];
    172 		cap_reset <= wdata[1];
    173 	end else begin
    174 		cap_reset <= 0;
    175 	end
    176 end
    177 
    178 endmodule