zybo_hdmi.sv (1977B)
1 // Copyright 2014 Brian Swetland <swetland@frotz.net> 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 `timescale 1ns / 1ps 16 17 module top( 18 input clk, 19 output [2:0]hdmi_d_p, 20 output [2:0]hdmi_d_n, 21 output hdmi_clk_p, 22 output hdmi_clk_n 23 ); 24 25 wire pixclk, pixclkx5, pixclkx10; 26 wire [10:0] xpixel, ypixel; 27 reg [7:0] red, grn, blu; 28 29 mmcm_1in_3out #( 30 .CLKIN_PERIOD(8.0), 31 .VCO_MUL(36.000), 32 .VCO_DIV(5), 33 .OUT0_DIV(20), // 45MHz 34 .OUT1_DIV(4), // 225MHz 35 .OUT2_DIV(2) // 450MHz 36 ) mmcm0 ( 37 .i_clk(clk), 38 .o_clk0(pixclk), 39 .o_clk1(pixclkx5), 40 .o_clk2(pixclkx10) 41 ); 42 43 hdmi_core #( 44 // 640x480 @60 25MHz 45 //.HWIDTH(640), .HSYNC0(656), .HSYNC1(752), .HMAX(799), 46 //.VHEIGHT(480), .VSYNC0(490), .VSYNC1(492), .VMAX(524) 47 // 1280x720 @60 75MHz 48 //.HWIDTH(1280), .HSYNC0(1320), .HSYNC1(1376). HMAX(1649), 49 //.VHEIGHT(720), .VSYNC0(722), .VSYNC1(728), .VMAX(750) 50 // 960x600 @60 45MHz 51 .HWIDTH(960), .HSYNC0(1000), .HSYNC1(1100), .HMAX(1199), 52 .VHEIGHT(600), .VSYNC0(613), .VSYNC1(620), .VMAX(624) 53 ) hdmi0 ( 54 .pixclk(pixclk), 55 .pixclkx5(pixclkx5), 56 .hdmi_d_p(hdmi_d_p), 57 .hdmi_d_n(hdmi_d_n), 58 .hdmi_clk_p(hdmi_clk_p), 59 .hdmi_clk_n(hdmi_clk_n), 60 .rgb_ready(), 61 .red(red), 62 .grn(grn), 63 .blu(blu), 64 .xpixel(xpixel), 65 .ypixel(ypixel), 66 .vblank() 67 ); 68 69 // test pattern 70 always @(posedge pixclk) begin 71 red <= xpixel[3] ? 8'hFF : 8'h00; 72 grn <= ypixel[3] ? 8'hFF : 8'h00; 73 blu <= ypixel[7:0]; 74 end 75 76 endmodule