zybo_hdmi_axi.sv (3754B)
1 // Copyright 2014 Brian Swetland <swetland@frotz.net> 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 `timescale 1ns / 1ps 16 17 module top( 18 input clk, 19 output [2:0]hdmi_d_p, 20 output [2:0]hdmi_d_n, 21 output hdmi_clk_p, 22 output hdmi_clk_n 23 ); 24 25 wire pixclk, pixclkx5, pixclkx10; 26 wire [10:0] xpixel, ypixel; 27 wire [7:0] red, grn, blu; 28 29 mmcm_1in_3out #( 30 .CLKIN_PERIOD(8.0), 31 .VCO_MUL(36.000), 32 .VCO_DIV(5), 33 .OUT0_DIV(20), // 45MHz 34 .OUT1_DIV(4), // 225MHz 35 .OUT2_DIV(2) // 450MHz 36 ) mmcm0 ( 37 .i_clk(clk), 38 .o_clk0(pixclk), 39 .o_clk1(pixclkx5), 40 .o_clk2(pixclkx10) 41 ); 42 43 wire rgb_ready; 44 wire vsync_raw; 45 46 hdmi_core #( 47 // 640x480 @60 25MHz 48 //.HWIDTH(640), .HSYNC0(656), .HSYNC1(752), .HMAX(799), 49 //.VHEIGHT(480), .VSYNC0(490), .VSYNC1(492), .VMAX(524) 50 // 1280x720 @60 75MHz 51 //.HWIDTH(1280), .HSYNC0(1320), .HSYNC1(1376). HMAX(1649), 52 //.VHEIGHT(720), .VSYNC0(722), .VSYNC1(728), .VMAX(750) 53 // 960x600 @60 45MHz 54 .HWIDTH(960), .HSYNC0(1000), .HSYNC1(1100), .HMAX(1199), 55 .VHEIGHT(600), .VSYNC0(613), .VSYNC1(620), .VMAX(624) 56 ) hdmi0 ( 57 .pixclk(pixclk), 58 .pixclkx5(pixclkx5), 59 .hdmi_d_p(hdmi_d_p), 60 .hdmi_d_n(hdmi_d_n), 61 .hdmi_clk_p(hdmi_clk_p), 62 .hdmi_clk_n(hdmi_clk_n), 63 .rgb_ready(rgb_ready), 64 .red(red), 65 .grn(grn), 66 .blu(blu), 67 .xpixel(xpixel), 68 .ypixel(ypixel), 69 .vblank(vsync_raw) 70 ); 71 72 wire axiclk; 73 wire vsync; 74 75 sync_oneway sync_vsync( 76 .txclk(pixclk), 77 .txdat(vsync_raw), 78 .rxclk(axiclk), 79 .rxdat(vsync) 80 ); 81 82 axi_ifc #(.IWIDTH(12),.AXI3(1)) axi_ctl(); 83 axi_ifc #(.IWIDTH(6),.AXI3(1)) axi_dma(); 84 85 zynq_ps7 zynq( 86 .fclk0(axiclk), 87 .m_axi_gp0_clk(axiclk), 88 .m_axi_gp0(axi_ctl), 89 .s_axi_gp0_clk(axiclk), 90 .s_axi_gp0(axi_dma) 91 ); 92 93 wire [31:0]wdata; 94 wire [1:0]wreg; 95 wire wr; 96 97 axi_registers regs( 98 .clk(axiclk), 99 .s(axi_ctl), 100 .o_rreg(), 101 .o_wreg(wreg), 102 .i_rdata(32'h12345678), 103 .o_wdata(wdata), 104 .o_rd(), 105 .o_wr(wr) 106 ); 107 108 wire [31:0]fb_data; 109 wire fb_valid; 110 reg fb_enable = 0; 111 wire fifo_ready; 112 113 axi_dma_reader reader( 114 .clk(axiclk), 115 .m(axi_dma), 116 .o_data(fb_data), 117 .o_valid(fb_valid), 118 .i_start(fb_enable & vsync), 119 .i_ready(fifo_ready), 120 .i_baseaddr(32'h10000000), 121 .i_burst_count(36000) 122 ); 123 124 reg fifo_reset = 0; 125 reg [23:0]pattern = 0; 126 127 reg cbufwe = 0; 128 reg [11:0]cbufaddr = 0; 129 reg [7:0]cbufdata = 0; 130 131 always_ff @(posedge axiclk) begin 132 if (wr) begin 133 case (wreg) 134 0: fifo_reset <= 1; 135 1: fb_enable <= wdata[0]; 136 2: pattern <= wdata[23:0]; 137 3: begin 138 cbufwe <= 1; 139 cbufaddr <= wdata[27:16]; 140 cbufdata <= wdata[7:0]; 141 end 142 endcase 143 end else begin 144 fifo_reset <= 0; 145 cbufwe <= 0; 146 end 147 end 148 149 wire text; 150 151 textdisplay textdisplay0( 152 .pixclk(pixclk), 153 .xpixel(xpixel), 154 .ypixel(ypixel), 155 .pixel(text), 156 .bufclk(axiclk), 157 .bufaddr(cbufaddr), 158 .bufdata(cbufdata), 159 .bufwe(cbufwe) 160 ); 161 162 wire [23:0]fifo_data; 163 wire fifo_empty; 164 165 assign {red,grn,blu} = text ? 24'hffffff : (fifo_empty ? pattern : fifo_data); 166 167 xilinx_async_fifo #(.WIDTH(24)) fifo( 168 .wrclk(axiclk), 169 .rdclk(pixclk), 170 .reset(fifo_reset), 171 .wr_data(fb_data[23:0]), 172 .wr_en(fb_valid), 173 .rd_data(fifo_data), 174 .rd_en(rgb_ready), 175 .o_empty(fifo_empty), 176 .o_ready(fifo_ready), 177 .o_active() 178 ); 179 180 endmodule