zybo_simple_io.sv (1520B)
1 // Copyright 2014 Brian Swetland <swetland@frotz.net> 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 `timescale 1ns / 1ps 16 17 module top( 18 input clk, 19 input [3:0]sw, 20 input [3:0]btn, 21 output reg [3:0]led = 0 22 ); 23 24 axi_ifc #(.IWIDTH(12),.AXI3(1)) axi_ctl(); 25 26 wire fclk; 27 wire axiclk = clk; 28 29 zynq_ps7 zynq( 30 .fclk0(fclk), 31 .m_axi_gp0_clk(axiclk), 32 .m_axi_gp0(axi_ctl) 33 ); 34 35 reg [31:0]dbg_reg = 32'haabbccdd; 36 37 wire [31:0]wdata; 38 reg [31:0]rdata; 39 wire [1:0]wreg; 40 wire [1:0]rreg; 41 wire wr; 42 wire rd; 43 44 axi_registers regs( 45 .clk(axiclk), 46 .s(axi_ctl), 47 .o_rreg(rreg), 48 .o_wreg(wreg), 49 .i_rdata(rdata), 50 .o_wdata(wdata), 51 .o_rd(rd), 52 .o_wr(wr) 53 ); 54 55 always_comb begin 56 case (rreg) 57 0: rdata = { 28'b0, sw }; 58 1: rdata = { 28'b0, btn }; 59 2: rdata = dbg_reg; 60 3: rdata = 32'h12345678; 61 endcase 62 end 63 64 always_ff @(posedge axiclk) begin 65 if (wr) begin 66 case (wreg) 67 0: led <= wdata[3:0]; 68 1: ; 69 2: dbg_reg <= wdata; 70 3: ; 71 endcase 72 end 73 end 74 75 endmodule