commit 0fc4438a057c6af563e3d22b8e4ecd2d59c0c692 parent 32ad4fd320efccddf493723eaa63c8816c14e31a Author: Brian Swetland <swetland@frotz.net> Date: Wed, 8 Feb 2012 14:49:05 -0800 de0nano: add modelsim setup to project Diffstat:
| M | de0nano/de0nano.qsf | | | 14 | +++++++++++--- |
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/de0nano/de0nano.qsf b/de0nano/de0nano.qsf @@ -233,6 +233,15 @@ set_global_assignment -name VERILOG_FILE de0nano.v set_global_assignment -name VERILOG_FILE aram.v set_global_assignment -name SDC_FILE de0nano.sdc set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" -set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top -\ No newline at end of file +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT ON -section_id eda_simulation +set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT ON -section_id eda_simulation +set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY ON -section_id eda_simulation +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation +set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH testbench -section_id eda_simulation +set_global_assignment -name EDA_TEST_BENCH_NAME testbench -section_id eda_simulation +set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id testbench +set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME testbench -section_id testbench +set_global_assignment -name EDA_TEST_BENCH_FILE testbench.v -section_id testbench +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top