cpu32

commit 25e0ca41100d9dde401ad4c86cfeb34f67b004cf
parent 405e532ec3ce4d70cb33e12d897c7de767e17050
Author: Brian Swetland <swetland@frotz.net>
Date:   Sun,  5 Feb 2012 08:09:09 -0800

testbench: provide a "teleprinter" @0xE0000000

Diffstat:
M
verilog/testbench.v
 | 
20
+++++++++++++++++++-

1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/verilog/testbench.v b/verilog/testbench.v
@@ -48,6 +48,13 @@ ram #(32,8) ram(
 	.we(ramwe)
 	);
 
+teleprinter io(
+	.clk(clk),
+	.we(ramwe),
+	.cs(ramaddr[31:28] == 4'hE),
+	.data(ramwdata[7:0])
+);
+
 initial begin
 	$dumpfile("testbench.vcd");
 	$dumpvars(0,testbench);
@@ -61,8 +68,19 @@ initial
 		cpu.REGS.R[0],
 		cpu.REGS.R[1],
 		cpu.REGS.R[2],
-		cpu.REGS.R[3]
+		cpu.REGS.R[15]
 		);
 
 endmodule
 
+module teleprinter (
+	input we,
+	input cs,
+	input clk,
+	input [7:0] data
+	);
+	always @(posedge clk)
+		if (cs & we)
+			$write("%c", data);
+endmodule
+