cpu32

commit 2b1d042deae6ee3f7ccafa1a86320266e6928ee4
parent 0c0908d965c48aa25b36a4262f6799e6039dab93
Author: Brian Swetland <swetland@frotz.net>
Date:   Wed,  8 Feb 2012 21:20:00 -0800

testbench: make tests run again

Diffstat:
M
verilog/testbench.v
 | 
20
+++++++++++---------

1 file changed, 11 insertions(+), 9 deletions(-)
diff --git a/verilog/testbench.v b/verilog/testbench.v
@@ -31,11 +31,12 @@ wire [7:0] urdata;
 
 cpu32 cpu(
 	.clk(clk),
-	.reset(reset),
+	.reset(0),
+//	.reset(reset),
 	.i_addr(romaddr),
 	.i_data(romdata),
-//	.d_data_r(ramrdata),
-	.d_data_r({24'b0,urdata}),
+	.d_data_r(ramrdata),
+//	.d_data_r({24'b0,urdata}),
 	.d_data_w(ramwdata),
 	.d_addr(ramaddr),
 	.d_we(ramwe)
@@ -54,8 +55,9 @@ ram #(32,8) ram(
 	.we(ramwe)
 	);
 
-wire tx;
 
+/*
+wire tx;
 uart uart0(
 	.clk(clk),
 	.reset(reset),
@@ -64,12 +66,12 @@ uart uart0(
 	.we(ramwe & (ramaddr[31:28] == 4'hE)),
 	.tx(tx)
 	);
-	
+*/
 
 teleprinter io(
 	.clk(clk),
 	.we(ramwe),
-	.cs(ramaddr[31:28] == 4'h8),
+	.cs(ramaddr[31:28] == 4'hE),
 	.data(ramwdata[7:0])
 );
 
@@ -78,9 +80,9 @@ initial begin
 	$dumpvars(0,testbench);
 end
 
-initial #1000000 $finish;
+initial #1000 $finish;
+
 
-/*
 always @(posedge clk) begin
 	if (cpu.ir == 32'hFFFFFFFF) begin
 		$display("PC> EXIT");
@@ -99,7 +101,7 @@ always @(posedge clk) begin
 		cpu.REGS.R[15]
 		);
 end
-*/
+
 endmodule
 
 module teleprinter (