commit 54cd39dd4d480954fb922a54bf32d2d428ed5a9f
parent 87063f35e0be358abab92bb980969b56bb7f9f32
Author: Brian Swetland <swetland@frotz.net>
Date: Sat, 18 Feb 2012 04:39:16 -0800
de0test: experiment with jtag and vga
Diffstat:
6 files changed, 909 insertions(+), 0 deletions(-)
diff --git a/.gitignore b/.gitignore
@@ -1,3 +1,4 @@
*.bak
de0nano/*
de0/*
+de0test/*
diff --git a/de0test/de0board.qpf b/de0test/de0board.qpf
@@ -0,0 +1 @@
+PROJECT_REVISION = "de0board"
diff --git a/de0test/de0board.qsf b/de0test/de0board.qsf
@@ -0,0 +1,538 @@
+
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE EP3C16F484C6
+set_global_assignment -name TOP_LEVEL_ENTITY de0board
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "8.0 SP1"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:06:14 MARCH 06, 2009"
+set_global_assignment -name LAST_QUARTUS_VERSION 11.1
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
+set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 14622752 -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+
+# Pin & Location Assignments
+# ==========================
+set_location_assignment PIN_B1 -to LEDG[9]
+set_location_assignment PIN_B2 -to LEDG[8]
+set_location_assignment PIN_C2 -to LEDG[7]
+set_location_assignment PIN_C1 -to LEDG[6]
+set_location_assignment PIN_E1 -to LEDG[5]
+set_location_assignment PIN_F2 -to LEDG[4]
+set_location_assignment PIN_H1 -to LEDG[3]
+set_location_assignment PIN_J3 -to LEDG[2]
+set_location_assignment PIN_J2 -to LEDG[1]
+set_location_assignment PIN_J1 -to LEDG[0]
+set_location_assignment PIN_D2 -to SW[9]
+set_location_assignment PIN_E4 -to SW[8]
+set_location_assignment PIN_E3 -to SW[7]
+set_location_assignment PIN_H7 -to SW[6]
+set_location_assignment PIN_J7 -to SW[5]
+set_location_assignment PIN_G5 -to SW[4]
+set_location_assignment PIN_G4 -to SW[3]
+set_location_assignment PIN_H6 -to SW[2]
+set_location_assignment PIN_H5 -to SW[1]
+set_location_assignment PIN_J6 -to SW[0]
+set_location_assignment PIN_F1 -to ORG_BUTTON[2]
+set_location_assignment PIN_G3 -to ORG_BUTTON[1]
+set_location_assignment PIN_H2 -to ORG_BUTTON[0]
+set_location_assignment PIN_R2 -to FL_ADDR[21]
+set_location_assignment PIN_P3 -to FL_ADDR[20]
+set_location_assignment PIN_P1 -to FL_ADDR[19]
+set_location_assignment PIN_M6 -to FL_ADDR[18]
+set_location_assignment PIN_M5 -to FL_ADDR[17]
+set_location_assignment PIN_AA2 -to FL_ADDR[16]
+set_location_assignment PIN_L6 -to FL_ADDR[15]
+set_location_assignment PIN_L7 -to FL_ADDR[14]
+set_location_assignment PIN_M1 -to FL_ADDR[13]
+set_location_assignment PIN_M2 -to FL_ADDR[12]
+set_location_assignment PIN_M3 -to FL_ADDR[11]
+set_location_assignment PIN_N1 -to FL_ADDR[10]
+set_location_assignment PIN_N2 -to FL_ADDR[9]
+set_location_assignment PIN_P2 -to FL_ADDR[8]
+set_location_assignment PIN_M4 -to FL_ADDR[7]
+set_location_assignment PIN_M8 -to FL_ADDR[6]
+set_location_assignment PIN_N6 -to FL_ADDR[5]
+set_location_assignment PIN_N5 -to FL_ADDR[4]
+set_location_assignment PIN_N7 -to FL_ADDR[3]
+set_location_assignment PIN_P6 -to FL_ADDR[2]
+set_location_assignment PIN_P5 -to FL_ADDR[1]
+set_location_assignment PIN_P7 -to FL_ADDR[0]
+set_location_assignment PIN_AA1 -to FL_BYTE_N
+set_location_assignment PIN_N8 -to FL_CE_N
+set_location_assignment PIN_R7 -to FL_DQ[0]
+set_location_assignment PIN_P8 -to FL_DQ[1]
+set_location_assignment PIN_R8 -to FL_DQ[2]
+set_location_assignment PIN_U1 -to FL_DQ[3]
+set_location_assignment PIN_V2 -to FL_DQ[4]
+set_location_assignment PIN_V3 -to FL_DQ[5]
+set_location_assignment PIN_W1 -to FL_DQ[6]
+set_location_assignment PIN_Y1 -to FL_DQ[7]
+set_location_assignment PIN_T5 -to FL_DQ[8]
+set_location_assignment PIN_T7 -to FL_DQ[9]
+set_location_assignment PIN_T4 -to FL_DQ[10]
+set_location_assignment PIN_U2 -to FL_DQ[11]
+set_location_assignment PIN_V1 -to FL_DQ[12]
+set_location_assignment PIN_V4 -to FL_DQ[13]
+set_location_assignment PIN_W2 -to FL_DQ[14]
+set_location_assignment PIN_R6 -to FL_OE_N
+set_location_assignment PIN_R1 -to FL_RST_N
+set_location_assignment PIN_M7 -to FL_RY
+set_location_assignment PIN_P4 -to FL_WE_N
+set_location_assignment PIN_T3 -to FL_WP_N
+set_location_assignment PIN_Y2 -to FL_DQ15_AM1
+set_location_assignment PIN_U7 -to GPIO0_D[31]
+set_location_assignment PIN_V5 -to GPIO0_D[30]
+set_location_assignment PIN_W6 -to GPIO0_D[29]
+set_location_assignment PIN_W7 -to GPIO0_D[28]
+set_location_assignment PIN_V8 -to GPIO0_D[27]
+set_location_assignment PIN_T8 -to GPIO0_D[26]
+set_location_assignment PIN_W10 -to GPIO0_D[25]
+set_location_assignment PIN_Y10 -to GPIO0_D[24]
+set_location_assignment PIN_V11 -to GPIO0_D[23]
+set_location_assignment PIN_R10 -to GPIO0_D[22]
+set_location_assignment PIN_V12 -to GPIO0_D[21]
+set_location_assignment PIN_U13 -to GPIO0_D[20]
+set_location_assignment PIN_W13 -to GPIO0_D[19]
+set_location_assignment PIN_Y13 -to GPIO0_D[18]
+set_location_assignment PIN_U14 -to GPIO0_D[17]
+set_location_assignment PIN_V14 -to GPIO0_D[16]
+set_location_assignment PIN_AA4 -to GPIO0_D[15]
+set_location_assignment PIN_AB4 -to GPIO0_D[14]
+set_location_assignment PIN_AA5 -to GPIO0_D[13]
+set_location_assignment PIN_AB5 -to GPIO0_D[12]
+set_location_assignment PIN_AA8 -to GPIO0_D[11]
+set_location_assignment PIN_AB8 -to GPIO0_D[10]
+set_location_assignment PIN_AA10 -to GPIO0_D[9]
+set_location_assignment PIN_AB10 -to GPIO0_D[8]
+set_location_assignment PIN_AA13 -to GPIO0_D[7]
+set_location_assignment PIN_AB13 -to GPIO0_D[6]
+set_location_assignment PIN_AB14 -to GPIO0_D[5]
+set_location_assignment PIN_AA14 -to GPIO0_D[4]
+set_location_assignment PIN_AB15 -to GPIO0_D[3]
+set_location_assignment PIN_AA15 -to GPIO0_D[2]
+set_location_assignment PIN_AA16 -to GPIO0_D[1]
+set_location_assignment PIN_AB16 -to GPIO0_D[0]
+set_location_assignment PIN_AB12 -to GPIO0_CLKIN[0]
+set_location_assignment PIN_AA12 -to GPIO0_CLKIN[1]
+set_location_assignment PIN_AB3 -to GPIO0_CLKOUT[0]
+set_location_assignment PIN_AA3 -to GPIO0_CLKOUT[1]
+set_location_assignment PIN_AA11 -to GPIO1_CLKIN[1]
+set_location_assignment PIN_AB11 -to GPIO1_CLKIN[0]
+set_location_assignment PIN_T16 -to GPIO1_CLKOUT[1]
+set_location_assignment PIN_R16 -to GPIO1_CLKOUT[0]
+set_location_assignment PIN_V7 -to GPIO1_D[31]
+set_location_assignment PIN_V6 -to GPIO1_D[30]
+set_location_assignment PIN_U8 -to GPIO1_D[29]
+set_location_assignment PIN_Y7 -to GPIO1_D[28]
+set_location_assignment PIN_T9 -to GPIO1_D[27]
+set_location_assignment PIN_U9 -to GPIO1_D[26]
+set_location_assignment PIN_T10 -to GPIO1_D[25]
+set_location_assignment PIN_U10 -to GPIO1_D[24]
+set_location_assignment PIN_R12 -to GPIO1_D[23]
+set_location_assignment PIN_R11 -to GPIO1_D[22]
+set_location_assignment PIN_T12 -to GPIO1_D[21]
+set_location_assignment PIN_U12 -to GPIO1_D[20]
+set_location_assignment PIN_R14 -to GPIO1_D[19]
+set_location_assignment PIN_T14 -to GPIO1_D[18]
+set_location_assignment PIN_AB7 -to GPIO1_D[17]
+set_location_assignment PIN_AA7 -to GPIO1_D[16]
+set_location_assignment PIN_AA9 -to GPIO1_D[15]
+set_location_assignment PIN_AB9 -to GPIO1_D[14]
+set_location_assignment PIN_V15 -to GPIO1_D[13]
+set_location_assignment PIN_W15 -to GPIO1_D[12]
+set_location_assignment PIN_T15 -to GPIO1_D[11]
+set_location_assignment PIN_U15 -to GPIO1_D[10]
+set_location_assignment PIN_W17 -to GPIO1_D[9]
+set_location_assignment PIN_Y17 -to GPIO1_D[8]
+set_location_assignment PIN_AB17 -to GPIO1_D[7]
+set_location_assignment PIN_AA17 -to GPIO1_D[6]
+set_location_assignment PIN_AA18 -to GPIO1_D[5]
+set_location_assignment PIN_AB18 -to GPIO1_D[4]
+set_location_assignment PIN_AB19 -to GPIO1_D[3]
+set_location_assignment PIN_AA19 -to GPIO1_D[2]
+set_location_assignment PIN_AB20 -to GPIO1_D[1]
+set_location_assignment PIN_AA20 -to GPIO1_D[0]
+set_location_assignment PIN_P22 -to PS2_KBCLK
+set_location_assignment PIN_P21 -to PS2_KBDAT
+set_location_assignment PIN_R21 -to PS2_MSCLK
+set_location_assignment PIN_R22 -to PS2_MSDAT
+set_location_assignment PIN_U22 -to UART_RXD
+set_location_assignment PIN_U21 -to UART_TXD
+set_location_assignment PIN_V22 -to UART_RTS
+set_location_assignment PIN_V21 -to UART_CTS
+set_location_assignment PIN_Y21 -to SD_CLK
+set_location_assignment PIN_Y22 -to SD_CMD
+set_location_assignment PIN_AA22 -to SD_DAT0
+set_location_assignment PIN_W21 -to SD_DAT3
+set_location_assignment PIN_W20 -to SD_WP_N
+set_location_assignment PIN_C20 -to LCD_DATA[7]
+set_location_assignment PIN_D20 -to LCD_DATA[6]
+set_location_assignment PIN_B21 -to LCD_DATA[5]
+set_location_assignment PIN_B22 -to LCD_DATA[4]
+set_location_assignment PIN_C21 -to LCD_DATA[3]
+set_location_assignment PIN_C22 -to LCD_DATA[2]
+set_location_assignment PIN_D21 -to LCD_DATA[1]
+set_location_assignment PIN_D22 -to LCD_DATA[0]
+set_location_assignment PIN_E22 -to LCD_RW
+set_location_assignment PIN_F22 -to LCD_RS
+set_location_assignment PIN_E21 -to LCD_EN
+set_location_assignment PIN_F21 -to LCD_BLON
+set_location_assignment PIN_J21 -to VGA_G[3]
+set_location_assignment PIN_K17 -to VGA_G[2]
+set_location_assignment PIN_J17 -to VGA_G[1]
+set_location_assignment PIN_H22 -to VGA_G[0]
+set_location_assignment PIN_L21 -to VGA_HS
+set_location_assignment PIN_L22 -to VGA_VS
+set_location_assignment PIN_H21 -to VGA_R[3]
+set_location_assignment PIN_H20 -to VGA_R[2]
+set_location_assignment PIN_H17 -to VGA_R[1]
+set_location_assignment PIN_H19 -to VGA_R[0]
+set_location_assignment PIN_K18 -to VGA_B[3]
+set_location_assignment PIN_J22 -to VGA_B[2]
+set_location_assignment PIN_K21 -to VGA_B[1]
+set_location_assignment PIN_K22 -to VGA_B[0]
+set_location_assignment PIN_G21 -to CLOCK_50
+set_location_assignment PIN_E11 -to HEX0_D[0]
+set_location_assignment PIN_F11 -to HEX0_D[1]
+set_location_assignment PIN_H12 -to HEX0_D[2]
+set_location_assignment PIN_H13 -to HEX0_D[3]
+set_location_assignment PIN_G12 -to HEX0_D[4]
+set_location_assignment PIN_F12 -to HEX0_D[5]
+set_location_assignment PIN_F13 -to HEX0_D[6]
+set_location_assignment PIN_D13 -to HEX0_DP
+set_location_assignment PIN_A15 -to HEX1_D[6]
+set_location_assignment PIN_E14 -to HEX1_D[5]
+set_location_assignment PIN_B14 -to HEX1_D[4]
+set_location_assignment PIN_A14 -to HEX1_D[3]
+set_location_assignment PIN_C13 -to HEX1_D[2]
+set_location_assignment PIN_B13 -to HEX1_D[1]
+set_location_assignment PIN_A13 -to HEX1_D[0]
+set_location_assignment PIN_B15 -to HEX1_DP
+set_location_assignment PIN_F14 -to HEX2_D[6]
+set_location_assignment PIN_B17 -to HEX2_D[5]
+set_location_assignment PIN_A17 -to HEX2_D[4]
+set_location_assignment PIN_E15 -to HEX2_D[3]
+set_location_assignment PIN_B16 -to HEX2_D[2]
+set_location_assignment PIN_A16 -to HEX2_D[1]
+set_location_assignment PIN_D15 -to HEX2_D[0]
+set_location_assignment PIN_A18 -to HEX2_DP
+set_location_assignment PIN_G15 -to HEX3_D[6]
+set_location_assignment PIN_D19 -to HEX3_D[5]
+set_location_assignment PIN_C19 -to HEX3_D[4]
+set_location_assignment PIN_B19 -to HEX3_D[3]
+set_location_assignment PIN_A19 -to HEX3_D[2]
+set_location_assignment PIN_F15 -to HEX3_D[1]
+set_location_assignment PIN_B18 -to HEX3_D[0]
+set_location_assignment PIN_G16 -to HEX3_DP
+set_location_assignment PIN_G8 -to DRAM_CAS_N
+set_location_assignment PIN_G7 -to DRAM_CS_N
+set_location_assignment PIN_E5 -to DRAM_CLK
+set_location_assignment PIN_E6 -to DRAM_CKE
+set_location_assignment PIN_B5 -to DRAM_BA_0
+set_location_assignment PIN_A4 -to DRAM_BA_1
+set_location_assignment PIN_F10 -to DRAM_DQ[15]
+set_location_assignment PIN_E10 -to DRAM_DQ[14]
+set_location_assignment PIN_A10 -to DRAM_DQ[13]
+set_location_assignment PIN_B10 -to DRAM_DQ[12]
+set_location_assignment PIN_C10 -to DRAM_DQ[11]
+set_location_assignment PIN_A9 -to DRAM_DQ[10]
+set_location_assignment PIN_B9 -to DRAM_DQ[9]
+set_location_assignment PIN_A8 -to DRAM_DQ[8]
+set_location_assignment PIN_F8 -to DRAM_DQ[7]
+set_location_assignment PIN_H9 -to DRAM_DQ[6]
+set_location_assignment PIN_G9 -to DRAM_DQ[5]
+set_location_assignment PIN_F9 -to DRAM_DQ[4]
+set_location_assignment PIN_E9 -to DRAM_DQ[3]
+set_location_assignment PIN_H10 -to DRAM_DQ[2]
+set_location_assignment PIN_G10 -to DRAM_DQ[1]
+set_location_assignment PIN_D10 -to DRAM_DQ[0]
+set_location_assignment PIN_E7 -to DRAM_LDQM
+set_location_assignment PIN_B8 -to DRAM_UDQM
+set_location_assignment PIN_F7 -to DRAM_RAS_N
+set_location_assignment PIN_D6 -to DRAM_WE_N
+set_location_assignment PIN_B12 -to CLOCK_50_2
+set_location_assignment PIN_C8 -to DRAM_ADDR[12]
+set_location_assignment PIN_A7 -to DRAM_ADDR[11]
+set_location_assignment PIN_B4 -to DRAM_ADDR[10]
+set_location_assignment PIN_B7 -to DRAM_ADDR[9]
+set_location_assignment PIN_C7 -to DRAM_ADDR[8]
+set_location_assignment PIN_A6 -to DRAM_ADDR[7]
+set_location_assignment PIN_B6 -to DRAM_ADDR[6]
+set_location_assignment PIN_C6 -to DRAM_ADDR[5]
+set_location_assignment PIN_A5 -to DRAM_ADDR[4]
+set_location_assignment PIN_C3 -to DRAM_ADDR[3]
+set_location_assignment PIN_B3 -to DRAM_ADDR[2]
+set_location_assignment PIN_A3 -to DRAM_ADDR[1]
+set_location_assignment PIN_C4 -to DRAM_ADDR[0]
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ORG_BUTTON[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ORG_BUTTON[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ORG_BUTTON[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_CE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_BYTE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_UDQM
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_LDQM
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[28]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[29]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[30]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[31]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKOUT[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKOUT[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKIN[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKIN[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[22]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[23]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[24]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[25]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[26]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[27]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[28]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[29]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[30]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[31]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKOUT[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKOUT[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKIN[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKIN[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WP_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RY
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RST_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_OE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ15_AM1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[22]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[23]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[24]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[25]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[26]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[27]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_BLON
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_CTS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_WP_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CMD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_MSDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_MSCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_KBDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_KBCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RW
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_EN
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RTS
+
+set_global_assignment -name ENABLE_ADVANCED_IO_TIMING ON
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
+
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+
+set_global_assignment -name VERILOG_FILE de0board.v
+set_global_assignment -name SDC_FILE de0board.sdc
+set_global_assignment -name VERILOG_FILE jtag.v
+set_global_assignment -name VERILOG_FILE ../verilog/chardata.v
+set_global_assignment -name VERILOG_FILE ../verilog/vga.v
+set_global_assignment -name VERILOG_FILE ../verilog/videoram.v
+
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+\ No newline at end of file
diff --git a/de0test/de0board.sdc b/de0test/de0board.sdc
@@ -0,0 +1,6 @@
+create_clock -period 20 [get_ports CLOCK_50]
+
+derive_pll_clocks
+
+derive_clock_uncertainty
+
diff --git a/de0test/de0board.v b/de0test/de0board.v
@@ -0,0 +1,181 @@
+// Copyright 2012, Brian Swetland
+
+module de0board(
+ input CLOCK_50,
+ output [9:0] LEDG,
+ output [6:0] HEX0_D,
+ output [6:0] HEX1_D,
+ output [6:0] HEX2_D,
+ output [6:0] HEX3_D,
+ output HEX0_DP,
+ output HEX1_DP,
+ output HEX2_DP,
+ output HEX3_DP,
+ output [3:0] VGA_R,
+ output [3:0] VGA_G,
+ output [3:0] VGA_B,
+ output VGA_HS,
+ output VGA_VS
+ );
+
+wire [15:0] status;
+reg [31:0] count;
+
+assign LEDG = 10'b1111111111;
+assign HEX0_DP = 1'b1;
+assign HEX1_DP = 1'b1;
+assign HEX2_DP = 1'b1;
+assign HEX3_DP = 1'b1;
+
+hex2seven hex0(.in(status[3:0]),.out(HEX0_D));
+hex2seven hex1(.in(status[7:4]),.out(HEX1_D));
+hex2seven hex2(.in(status[11:8]),.out(HEX2_D));
+hex2seven hex3(.in(status[15:12]),.out(HEX3_D));
+
+wire clk;
+assign clk = CLOCK_50;
+
+reg clk25;
+
+always @(posedge clk)
+ clk25 = ~clk25;
+
+wire newline, advance;
+wire [11:0] pixel;
+wire [10:0] vram_addr;
+wire [7:0] vram_data;
+wire [7:0] line;
+
+vga vga(
+ .clk(clk25),
+ .reset(1'b0),
+ .newline(newline),
+ .advance(advance),
+ .line(line),
+ .pixel(pixel),
+ .r(VGA_R),
+ .b(VGA_B),
+ .g(VGA_G),
+ .hs(VGA_HS),
+ .vs(VGA_VS)
+ );
+
+pixeldata pxd(
+ .clk(clk25),
+ .newline(newline),
+ .advance(advance),
+ .line(line),
+ .pixel(pixel),
+ .vram_data(vram_data),
+ .vram_addr(vram_addr)
+ );
+
+//assign status = 16'h1234;
+
+wire [7:0] wdata;
+reg [10:0] waddr;
+wire we;
+
+videoram #(8,11) vram(
+ .clk(clk),
+ .we(we),
+ .rdata(vram_data),
+ .raddr(vram_addr),
+ .wdata(wdata),
+ .waddr(waddr)
+ );
+
+wire [3:0] iir;
+wire tdi, tdo, tck, cdr, sdr, udr, uir;
+reg [15:0] dr;
+reg [3:0] ir;
+
+jtag jtag0(
+ .tdi(tdi),
+ .tdo(tdo),
+ .tck(tck),
+ .ir_in(iir),
+ .virtual_state_cdr(cdr),
+ .virtual_state_sdr(sdr),
+ .virtual_state_udr(udr),
+ .virtual_state_uir(uir)
+ );
+
+parameter IR_ADDR = 4'h1;
+parameter IR_DATA = 4'h2;
+
+always @(posedge tck) begin
+ if (uir)
+ ir <= iir;
+ if (cdr)
+ dr <= 16'hABCD;
+ if (sdr)
+ dr <= { tdi, dr[15:1] };
+ end
+assign tdo = dr[0];
+
+wire update;
+
+sync sync0(
+ .in(udr),
+ .clk_in(tck),
+ .out(update),
+ .clk_out(clk)
+ );
+
+assign wdata = dr[7:0];
+assign we = update & (ir == IR_DATA);
+
+always @(posedge clk)
+ if (update) case (iir)
+ IR_ADDR: waddr <= dr[10:0];
+ IR_DATA: waddr <= waddr + 11'd1;
+ endcase
+
+reg [31:0] dispreg;
+assign status = dispreg[15:0];
+
+endmodule
+
+module sync(
+ input clk_in,
+ input clk_out,
+ input in,
+ output out
+ );
+reg toggle;
+reg [2:0] sync;
+always @(posedge clk_in)
+ if (in) toggle <= ~toggle;
+always @(posedge clk_out)
+ sync <= { sync[1:0], toggle };
+assign out = (sync[2] ^ sync[1]);
+endmodule
+
+
+module hex2seven(
+ input [3:0] in,
+ output reg [6:0] out
+ );
+
+always @(*) case (in)
+ 4'h0: out = 7'b1000000;
+ 4'h1: out = 7'b1111001;
+ 4'h2: out = 7'b0100100;
+ 4'h3: out = 7'b0110000;
+ 4'h4: out = 7'b0011001;
+ 4'h5: out = 7'b0010010;
+ 4'h6: out = 7'b0000011;
+ 4'h7: out = 7'b1111000;
+ 4'h8: out = 7'b0000000;
+ 4'h9: out = 7'b0011000;
+ 4'hA: out = 7'b0001000;
+ 4'hB: out = 7'b0000011;
+ 4'hC: out = 7'b1000110;
+ 4'hD: out = 7'b0100001;
+ 4'hE: out = 7'b0000110;
+ 4'hF: out = 7'b0001110;
+endcase
+
+endmodule
+
diff --git a/de0test/jtag.v b/de0test/jtag.v
@@ -0,0 +1,181 @@
+// megafunction wizard: %Virtual JTAG%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: sld_virtual_jtag
+
+// ============================================================
+// File Name: jtag.v
+// Megafunction Name(s):
+// sld_virtual_jtag
+//
+// Simulation Library Files(s):
+// altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 11.1 Build 173 11/01/2011 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2011 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module jtag (
+ ir_out,
+ tdo,
+ ir_in,
+ tck,
+ tdi,
+ virtual_state_cdr,
+ virtual_state_cir,
+ virtual_state_e1dr,
+ virtual_state_e2dr,
+ virtual_state_pdr,
+ virtual_state_sdr,
+ virtual_state_udr,
+ virtual_state_uir);
+
+ input [3:0] ir_out;
+ input tdo;
+ output [3:0] ir_in;
+ output tck;
+ output tdi;
+ output virtual_state_cdr;
+ output virtual_state_cir;
+ output virtual_state_e1dr;
+ output virtual_state_e2dr;
+ output virtual_state_pdr;
+ output virtual_state_sdr;
+ output virtual_state_udr;
+ output virtual_state_uir;
+
+ wire sub_wire0;
+ wire sub_wire1;
+ wire [3:0] sub_wire2;
+ wire sub_wire3;
+ wire sub_wire4;
+ wire sub_wire5;
+ wire sub_wire6;
+ wire sub_wire7;
+ wire sub_wire8;
+ wire sub_wire9;
+ wire sub_wire10;
+ wire virtual_state_cir = sub_wire0;
+ wire virtual_state_pdr = sub_wire1;
+ wire [3:0] ir_in = sub_wire2[3:0];
+ wire tdi = sub_wire3;
+ wire virtual_state_udr = sub_wire4;
+ wire tck = sub_wire5;
+ wire virtual_state_e1dr = sub_wire6;
+ wire virtual_state_uir = sub_wire7;
+ wire virtual_state_cdr = sub_wire8;
+ wire virtual_state_e2dr = sub_wire9;
+ wire virtual_state_sdr = sub_wire10;
+
+ sld_virtual_jtag sld_virtual_jtag_component (
+ .ir_out (ir_out),
+ .tdo (tdo),
+ .virtual_state_cir (sub_wire0),
+ .virtual_state_pdr (sub_wire1),
+ .ir_in (sub_wire2),
+ .tdi (sub_wire3),
+ .virtual_state_udr (sub_wire4),
+ .tck (sub_wire5),
+ .virtual_state_e1dr (sub_wire6),
+ .virtual_state_uir (sub_wire7),
+ .virtual_state_cdr (sub_wire8),
+ .virtual_state_e2dr (sub_wire9),
+ .virtual_state_sdr (sub_wire10)
+ // synopsys translate_off
+ ,
+ .jtag_state_cdr (),
+ .jtag_state_cir (),
+ .jtag_state_e1dr (),
+ .jtag_state_e1ir (),
+ .jtag_state_e2dr (),
+ .jtag_state_e2ir (),
+ .jtag_state_pdr (),
+ .jtag_state_pir (),
+ .jtag_state_rti (),
+ .jtag_state_sdr (),
+ .jtag_state_sdrs (),
+ .jtag_state_sir (),
+ .jtag_state_sirs (),
+ .jtag_state_tlr (),
+ .jtag_state_udr (),
+ .jtag_state_uir (),
+ .tms ()
+ // synopsys translate_on
+ );
+ defparam
+ sld_virtual_jtag_component.sld_auto_instance_index = "NO",
+ sld_virtual_jtag_component.sld_instance_index = 0,
+ sld_virtual_jtag_component.sld_ir_width = 4,
+ sld_virtual_jtag_component.sld_sim_action = "",
+ sld_virtual_jtag_component.sld_sim_n_scan = 0,
+ sld_virtual_jtag_component.sld_sim_total_length = 0;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: PRIVATE: show_jtag_state STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: SLD_AUTO_INSTANCE_INDEX STRING "NO"
+// Retrieval info: CONSTANT: SLD_INSTANCE_INDEX NUMERIC "0"
+// Retrieval info: CONSTANT: SLD_IR_WIDTH NUMERIC "4"
+// Retrieval info: CONSTANT: SLD_SIM_ACTION STRING ""
+// Retrieval info: CONSTANT: SLD_SIM_N_SCAN NUMERIC "0"
+// Retrieval info: CONSTANT: SLD_SIM_TOTAL_LENGTH NUMERIC "0"
+// Retrieval info: USED_PORT: ir_in 0 0 4 0 OUTPUT NODEFVAL "ir_in[3..0]"
+// Retrieval info: USED_PORT: ir_out 0 0 4 0 INPUT NODEFVAL "ir_out[3..0]"
+// Retrieval info: USED_PORT: tck 0 0 0 0 OUTPUT NODEFVAL "tck"
+// Retrieval info: USED_PORT: tdi 0 0 0 0 OUTPUT NODEFVAL "tdi"
+// Retrieval info: USED_PORT: tdo 0 0 0 0 INPUT NODEFVAL "tdo"
+// Retrieval info: USED_PORT: virtual_state_cdr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_cdr"
+// Retrieval info: USED_PORT: virtual_state_cir 0 0 0 0 OUTPUT NODEFVAL "virtual_state_cir"
+// Retrieval info: USED_PORT: virtual_state_e1dr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_e1dr"
+// Retrieval info: USED_PORT: virtual_state_e2dr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_e2dr"
+// Retrieval info: USED_PORT: virtual_state_pdr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_pdr"
+// Retrieval info: USED_PORT: virtual_state_sdr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_sdr"
+// Retrieval info: USED_PORT: virtual_state_udr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_udr"
+// Retrieval info: USED_PORT: virtual_state_uir 0 0 0 0 OUTPUT NODEFVAL "virtual_state_uir"
+// Retrieval info: CONNECT: @ir_out 0 0 4 0 ir_out 0 0 4 0
+// Retrieval info: CONNECT: @tdo 0 0 0 0 tdo 0 0 0 0
+// Retrieval info: CONNECT: ir_in 0 0 4 0 @ir_in 0 0 4 0
+// Retrieval info: CONNECT: tck 0 0 0 0 @tck 0 0 0 0
+// Retrieval info: CONNECT: tdi 0 0 0 0 @tdi 0 0 0 0
+// Retrieval info: CONNECT: virtual_state_cdr 0 0 0 0 @virtual_state_cdr 0 0 0 0
+// Retrieval info: CONNECT: virtual_state_cir 0 0 0 0 @virtual_state_cir 0 0 0 0
+// Retrieval info: CONNECT: virtual_state_e1dr 0 0 0 0 @virtual_state_e1dr 0 0 0 0
+// Retrieval info: CONNECT: virtual_state_e2dr 0 0 0 0 @virtual_state_e2dr 0 0 0 0
+// Retrieval info: CONNECT: virtual_state_pdr 0 0 0 0 @virtual_state_pdr 0 0 0 0
+// Retrieval info: CONNECT: virtual_state_sdr 0 0 0 0 @virtual_state_sdr 0 0 0 0
+// Retrieval info: CONNECT: virtual_state_udr 0 0 0 0 @virtual_state_udr 0 0 0 0
+// Retrieval info: CONNECT: virtual_state_uir 0 0 0 0 @virtual_state_uir 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL jtag.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL jtag.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL jtag.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL jtag.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL jtag_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL jtag_bb.v FALSE
+// Retrieval info: LIB_FILE: altera_mf
