commit cac7e935da231e70b43021e547e101e83f8ac6d5
parent 20e6107dd598d7bfc630937ca5b0ec5f6000cd19
Author: Brian Swetland <swetland@frotz.net>
Date: Thu, 9 Feb 2012 17:36:56 -0800
de0nano: use sram, not sync
Diffstat:
2 files changed, 7 insertions(+), 179 deletions(-)
diff --git a/de0nano/aram.v b/de0nano/aram.v
@@ -1,172 +0,0 @@
-// megafunction wizard: %RAM: 1-PORT%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: altsyncram
-
-// ============================================================
-// File Name: aram.v
-// Megafunction Name(s):
-// altsyncram
-//
-// Simulation Library Files(s):
-// altera_mf
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-//
-// 11.1 Build 216 11/23/2011 SP 1 SJ Web Edition
-// ************************************************************
-
-
-//Copyright (C) 1991-2011 Altera Corporation
-//Your use of Altera Corporation's design tools, logic functions
-//and other software and tools, and its AMPP partner logic
-//functions, and any output files from any of the foregoing
-//(including device programming or simulation files), and any
-//associated documentation or information are expressly subject
-//to the terms and conditions of the Altera Program License
-//Subscription Agreement, Altera MegaCore Function License
-//Agreement, or other applicable license agreement, including,
-//without limitation, that your use is for the sole purpose of
-//programming logic devices manufactured by Altera and sold by
-//Altera or its authorized distributors. Please refer to the
-//applicable agreement for further details.
-
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-module aram (
- address,
- clock,
- data,
- wren,
- q);
-
- input [8:0] address;
- input clock;
- input [31:0] data;
- input wren;
- output [31:0] q;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_off
-`endif
- tri1 clock;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_on
-`endif
-
- wire [31:0] sub_wire0;
- wire [31:0] q = sub_wire0[31:0];
-
- altsyncram altsyncram_component (
- .address_a (address),
- .clock0 (clock),
- .data_a (data),
- .wren_a (wren),
- .q_a (sub_wire0),
- .aclr0 (1'b0),
- .aclr1 (1'b0),
- .address_b (1'b1),
- .addressstall_a (1'b0),
- .addressstall_b (1'b0),
- .byteena_a (1'b1),
- .byteena_b (1'b1),
- .clock1 (1'b1),
- .clocken0 (1'b1),
- .clocken1 (1'b1),
- .clocken2 (1'b1),
- .clocken3 (1'b1),
- .data_b (1'b1),
- .eccstatus (),
- .q_b (),
- .rden_a (1'b1),
- .rden_b (1'b1),
- .wren_b (1'b0));
- defparam
- altsyncram_component.clock_enable_input_a = "BYPASS",
- altsyncram_component.clock_enable_output_a = "BYPASS",
- altsyncram_component.intended_device_family = "Cyclone IV E",
- altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
- altsyncram_component.lpm_type = "altsyncram",
- altsyncram_component.numwords_a = 512,
- altsyncram_component.operation_mode = "SINGLE_PORT",
- altsyncram_component.outdata_aclr_a = "NONE",
- altsyncram_component.outdata_reg_a = "CLOCK0",
- altsyncram_component.power_up_uninitialized = "FALSE",
- altsyncram_component.read_during_write_mode_port_a = "DONT_CARE",
- altsyncram_component.widthad_a = 9,
- altsyncram_component.width_a = 32,
- altsyncram_component.width_byteena_a = 1;
-
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-// Retrieval info: PRIVATE: AclrData NUMERIC "0"
-// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-// Retrieval info: PRIVATE: Clken NUMERIC "0"
-// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-// Retrieval info: PRIVATE: MIFfilename STRING ""
-// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "512"
-// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "2"
-// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-// Retrieval info: PRIVATE: RegData NUMERIC "1"
-// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-// Retrieval info: PRIVATE: WidthAddr NUMERIC "9"
-// Retrieval info: PRIVATE: WidthData NUMERIC "32"
-// Retrieval info: PRIVATE: rden NUMERIC "0"
-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
-// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "DONT_CARE"
-// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
-// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
-// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-// Retrieval info: USED_PORT: address 0 0 9 0 INPUT NODEFVAL "address[8..0]"
-// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
-// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
-// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-// Retrieval info: CONNECT: @address_a 0 0 9 0 address 0 0 9 0
-// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
-// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-// Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
-// Retrieval info: GEN_FILE: TYPE_NORMAL aram.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL aram.inc FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL aram.cmp FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL aram.bsf FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL aram_inst.v FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL aram_bb.v TRUE
-// Retrieval info: LIB_FILE: altera_mf
diff --git a/de0nano/de0nano.v b/de0nano/de0nano.v
@@ -61,13 +61,13 @@ rom rom(
.data(romdata)
);
-aram ram(
- .clock(clk),
- .address(ramaddr[10:2]),
- .data(ramwdata),
- .q(ramrdata),
- .wren(cs0 & ramwe)
-);
+ram #(32,8) ram(
+ .clk(clk),
+ .addr(ramaddr[9:2]),
+ .rdata(ramrdata),
+ .wdata(ramwdata),
+ .we(ramwe)
+ );
uart uart0(
.clk(clk),
