cpu32

commit d6cc6079f42aa2410ea789674a914ce9b4354225
parent eb0e0c09f25b7c00f537c80e2154cdd80410298c
Author: Brian Swetland <swetland@frotz.net>
Date:   Sun,  5 Feb 2012 18:59:46 -0800

uart: work in progress

Diffstat:
M
verilog/uart.v
 | 
41
+++++++++++++++++------------------------

1 file changed, 17 insertions(+), 24 deletions(-)
diff --git a/verilog/uart.v b/verilog/uart.v
@@ -4,53 +4,46 @@
 
 module uart(
 	input clk,
+	input bclk,
 	input reset,
-	input [8:0] bdiv,
 	input [7:0] wdata,
+	output [7:0] rdata,
 	input we,
 	output tx
 	);
 
-reg bclk;
-reg [8:0] bcnt;
-reg [7:0] thr;
-
 reg [7:0] tx_fifo;
-reg [10:0] tx_shift;
+reg [12:0] tx_shift;
+reg [3:0] tx_count;
+
 wire tx_busy;
 reg tx_start;
 
+assign rdata = { 7'h0, tx_busy };
 assign tx = tx_shift[0];
-
-assign tx_busy = (tx_shift[10:1] != 0);
+assign tx_busy = (tx_count != 0);
 
 always @(posedge bclk, posedge reset) begin
-	if (reset)
-		tx_shift <= 11'h001;
-	else if (tx_busy) 
-		tx_shift = { 1'b0, tx_shift[10:1] };
-	else if (tx_start) begin
-		tx_shift <= { 1'b1, tx_fifo, 2'b01 };
+	if (reset) begin
+		tx_count <= 0;
+		tx_shift <= 13'hFFFF;
+	end else if (tx_busy) begin
+		tx_shift <= { 1'b0, tx_shift[12:1] };
+		tx_count <= ( tx_count - 1 );
+	end else if (tx_start) begin
+		tx_shift[12:1] <= { 2'b11, tx_fifo, 1'b0 };
+		tx_count <= 11;
 	end
 end
 
 always @(posedge clk) begin
 	if (reset) begin
-		bcnt <= 0;
-		bclk <= 0;
 		tx_start <= 0;
 	end else begin
-		if (bcnt == bdiv) begin
-			bcnt <= 9'h0;
-			bclk <= !bclk;
-		end else begin
-			bcnt <= bcnt + 1;
-			bclk <= bclk;
-		end
 		if (tx_busy)
 			tx_start <= 0;
 		else if (we) begin
-			tx_fifo = wdata;
+			tx_fifo <= wdata;
 			tx_start <= 1;
 		end
 	end