cpu32

commit df7f05564ddf620edb5e44bdf61705f96449127e
parent 0b4cfa6755e71fc2232cd42fdfd9976e9d0dbe6e
Author: Brian Swetland <swetland@frotz.net>
Date:   Sun,  5 Feb 2012 10:34:18 -0800

testbench: commandling ROM parameter and EXIT support

- use +ROM=path/to/rom.txt to specify a ROM image to use
- use the illegal instruction FFFFFFFF to EXIT
- use the illegal instruction FFFFFFFE to ERROR out

Diffstat:
M
verilog/rom.v
 | 
7
++++++-
M
verilog/testbench.v
 | 
18
++++++++++++++----

2 files changed, 20 insertions(+), 5 deletions(-)
diff --git a/verilog/rom.v b/verilog/rom.v
@@ -12,8 +12,13 @@ module rom #(parameter DWIDTH=16, parameter AWIDTH=8) (
 
 	reg [DWIDTH-1:0] rom[0:2**AWIDTH-1];
 
+	reg [256:0] romfile;
+
 	initial
-		$readmemh("rom.txt", rom);
+		if ($value$plusargs("ROM=%s",romfile))
+			$readmemh(romfile, rom);
+		else
+			$readmemh("rom.txt", rom);
 
 	assign data = rom[addr];
 endmodule
diff --git a/verilog/testbench.v b/verilog/testbench.v
@@ -60,16 +60,26 @@ initial begin
 	$dumpvars(0,testbench);
 end
 
-initial #400 $finish;
+initial #1000 $finish;
 
-initial
-	$monitor("%05t: pc=%h ir=%h R> %h %h %h %h",
-		$time, cpu.pc, cpu.ir,
+always @(posedge clk) begin
+	if (cpu.ir == 32'hFFFFFFFF) begin
+		$display("PC> EXIT");
+		$finish();
+	end
+	if (cpu.ir == 32'hFFFFFFFE) begin
+		$display("PC> ERROR");
+		$finish();
+	end
+	$display("PC> %h I> %h  R> %h %h %h %h %h",
+		cpu.pc, cpu.ir,
 		cpu.REGS.R[0],
 		cpu.REGS.R[1],
 		cpu.REGS.R[2],
+		cpu.REGS.R[14],
 		cpu.REGS.R[15]
 		);
+end
 
 endmodule