commit 0ade8e45ef87b061caf44ab04165340d8200a99a
parent 7325aaa9c7a3926d1db2d5b5da6e602fd13e0436
Author: Brian Swetland <swetland@frotz.net>
Date: Tue, 18 Dec 2018 17:22:26 -0800
vga40x30: add new "full rgb" mode
If built with parameter RGB set to 1, video ram is 16 bits wide,
the low 8 bits are the character id, the top 4 bits are the fg
color and the next 4 bits are the bg color (only the 3 LSB are
used in each case, RGB)
Diffstat:
3 files changed, 44 insertions(+), 15 deletions(-)
diff --git a/hdl/system_cpu16_vga40x30.v b/hdl/system_cpu16_vga40x30.v
@@ -175,7 +175,8 @@ wire [BPP-1:0]vg;
wire [BPP-1:0]vb;
vga40x30x2 #(
- .BPP(BPP)
+ .BPP(BPP),
+ .RGB(0)
) vga (
.clk25m(clk25m),
.red(vr),
@@ -186,7 +187,7 @@ vga40x30x2 #(
.fr(),
.active(vga_active),
.vram_waddr(waddr[10:0]),
- .vram_wdata(wdata[7:0]),
+ .vram_wdata(wdata[15:0]),
.vram_we(we & w_cs_vram),
.vram_clk(sys_clk)
);
diff --git a/hdl/vga/chardata.v b/hdl/vga/chardata.v
@@ -14,20 +14,18 @@
`timescale 1ns/1ns
module pixeldata #(
- parameter BPP = 2
+ parameter BPP = 2,
+ parameter RGB = 0
)(
input clk,
input newline,
input advance,
input [7:0] line,
output [(3*BPP)-1:0] pixel,
- input [7:0] vram_data,
+ input [(RGB*8)+7:0] vram_data,
output [10:0] vram_addr
);
-wire [(3*BPP)-1:0]FG = { 3*BPP { 1'b1 }};
-wire [(3*BPP)-1:0]BG = { { 2*BPP { 1'b0 }}, { BPP { 1'b1 }} };
-
reg [7:0] pattern_rom [0:1023];
`ifdef HEX_PATHS
@@ -54,8 +52,23 @@ reg [5:0]xpos = 6'b0;
reg [3:0]ppos = 4'b0;
reg [15:0]pattern = 16'b0;
-reg [7:0]cdata;
+reg [(RGB*8)+7:0]cdata;
reg [7:0]pdata;
+reg [2:0]fg;
+reg [2:0]bg;
+
+reg set_fg_bg;
+
+wire [(3*BPP)-1:0]FG;
+wire [(3*BPP)-1:0]BG;
+
+if (RGB) begin
+ assign FG = {{BPP{fg[2]}},{BPP{fg[1]}},{BPP{fg[0]}}};
+ assign BG = {{BPP{bg[2]}},{BPP{bg[1]}},{BPP{bg[0]}}};
+end else begin
+ assign FG = { 3*BPP { 1'b1 }};
+ assign BG = { { 2*BPP { 1'b0 }}, { BPP { 1'b1 }} };
+end
// generate vram address by using the high bits of the display
// line and the local xpos character counter
@@ -87,6 +100,7 @@ wire [15:0]pdata2x = {
assign pixel = pattern[15] ? FG : BG;
always_comb begin
+ set_fg_bg = 1'b0;
next_xpos = xpos;
next_ppos = ppos;
next_pattern = pattern;
@@ -109,6 +123,7 @@ always_comb begin
if (ppos == 4'hF) begin
// advance to next pattern (preloaded in pdata)
next_pattern = pdata2x;
+ set_fg_bg = 1'b1;
end else begin
// advance to the next bit in the current pattern
next_pattern = { pattern[14:0], 1'b0 };
@@ -122,8 +137,10 @@ always_comb begin
end else begin
// handle the final step of preloading the pattern
// for xpos 0 (between newline=1 and advance=1)
- if (load_pattern)
+ if (load_pattern) begin
next_pattern = pdata2x;
+ set_fg_bg = 1'b1;
+ end
end
end
@@ -142,4 +159,13 @@ always_ff @(posedge clk) begin
pdata <= prom_data;
end
+if (RGB) begin
+ always_ff @(posedge clk) begin
+ if (set_fg_bg) begin
+ fg <= cdata[14:12];
+ bg <= cdata[10:8];
+ end
+ end
+end
+
endmodule
diff --git a/hdl/vga/vga40x30x2.v b/hdl/vga/vga40x30x2.v
@@ -4,7 +4,8 @@
`default_nettype none
module vga40x30x2 #(
- parameter BPP = 2
+ parameter BPP = 2,
+ parameter RGB = 0
)(
input clk25m,
output [BPP-1:0]red,
@@ -16,7 +17,7 @@ module vga40x30x2 #(
output active,
input vram_clk,
input [10:0]vram_waddr,
- input [7:0]vram_wdata,
+ input [15:0]vram_wdata,
input vram_we
);
@@ -44,10 +45,11 @@ vga #(
assign active = advance;
wire [10:0]vram_raddr;
-wire [7:0]vram_rdata;
+wire [(RGB*8)+7:0]vram_rdata;
pixeldata #(
- .BPP(BPP)
+ .BPP(BPP),
+ .RGB(RGB)
) pixeldata0 (
.clk(clk25m),
.newline(newline),
@@ -58,14 +60,14 @@ pixeldata #(
.vram_addr(vram_raddr)
);
-videoram #(8,11) vram(
+videoram #((RGB*8)+8,11) vram(
.rclk(clk25m),
.re(1'b1),
.rdata(vram_rdata),
.raddr(vram_raddr),
.wclk(vram_clk),
.we(vram_we),
- .wdata(vram_wdata[7:0]),
+ .wdata(vram_wdata[(RGB*8)+7:0]),
.waddr(vram_waddr[10:0])
);
