commit 0d4b06f5abe5edd5907c0485f7cdf568f1019cbc
parent 2b9227d768755b5e22ea411875f50c4f3a33fa12
Author: Brian Swetland <swetland@frotz.net>
Date: Wed, 21 Nov 2018 13:01:55 -0800
vga: expose frame sync signal for use in testbenches
This is asserted on the first pixel clock of each new video
frame, giving testbench software a simpler way of figuring out
what the vga engine is doing than working backwards from hsync
and vsync.
Diffstat:
3 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/hdl/ice40.v b/hdl/ice40.v
@@ -128,6 +128,7 @@ vga40x30x2 vga(
.blu(vb),
.hs(vga_hsync),
.vs(vga_vsync),
+ .fr(),
.vram_waddr(waddr[10:0]),
.vram_wdata(wdata[7:0]),
.vram_we(we & cs_vram),
diff --git a/hdl/vga/vga.v b/hdl/vga/vga.v
@@ -11,6 +11,7 @@ module vga(
input clk,
output hs,
output vs,
+ output fr,
output [3:0] r,
output [3:0] g,
output [3:0] b,
@@ -21,15 +22,17 @@ module vga(
input [11:0] pixel
);
-reg hsync;
-reg vsync;
-reg active;
-reg startline;
+reg hsync = 1'b0;
+reg vsync = 1'b0;
+reg frame = 1'b0;
+reg active = 1'b0;
+reg startline = 1'b0;
reg [9:0] hcount = 10'b0;
reg [9:0] vcount = 10'b0;
reg next_hsync;
reg next_vsync;
+reg next_frame;
reg next_active;
reg next_startline;
reg [9:0] next_hcount;
@@ -39,6 +42,7 @@ reg [7:0] lineno;
assign hs = hsync;
assign vs = vsync;
+assign fr = frame;
assign line = lineno;
assign advance = active;
assign newline = startline;
@@ -50,6 +54,7 @@ assign b = active ? pixel[3:0] : 4'd0;
always_comb begin
next_hsync = 1'b0;
next_vsync = 1'b0;
+ next_frame = 1'b0;
next_hcount = 10'd0;
next_vcount = 10'd0;
next_active = 1'b0;
@@ -57,9 +62,10 @@ always_comb begin
next_lineno = 10'b0;
if (hcount == 10'd799) begin
- if (vcount == 10'd523)
+ if (vcount == 10'd523) begin
next_vcount = 10'd0;
- else
+ next_frame = 1'b1;
+ end else
next_vcount = vcount + 10'd1;
next_hcount = 10'd0;
end else begin
@@ -94,6 +100,7 @@ always_ff @(posedge clk) begin
vcount <= next_vcount;
hsync <= next_hsync;
vsync <= next_vsync;
+ frame <= next_frame;
/* signals to pixel generator */
startline <= next_startline;
diff --git a/hdl/vga/vga40x30x2.v b/hdl/vga/vga40x30x2.v
@@ -6,6 +6,7 @@ module vga40x30x2(
output [1:0]blu,
output hs,
output vs,
+ output fr,
input vram_clk,
input [10:0]vram_waddr,
input [7:0]vram_wdata,
@@ -25,6 +26,7 @@ vga vga0(
.clk(clk25m),
.hs(hs),
.vs(vs),
+ .fr(fr),
.r(r),
.g(g),
.b(b),
