gateware

commit 336385679fbec9df5ce62c52c81cd068cc1aa087
parent 3189205c14b6d5d170db277faea41dd8c463e6fd
Author: Brian Swetland <swetland@frotz.net>
Date:   Tue, 29 Dec 2015 22:10:57 -0800

make test target and some tests

Diffstat:
M
Makefile
 | 
14
++++++++++++++
A
tests/000_load_registers.s
 | 
20
++++++++++++++++++++
A
tests/001_simple_loop.s
 | 
19
+++++++++++++++++++
A
tests/runtest
 | 
35
+++++++++++++++++++++++++++++++++++

4 files changed, 88 insertions(+), 0 deletions(-)
diff --git a/Makefile b/Makefile
@@ -31,6 +31,20 @@ out/d16: src/d16.c
 	@mkdir -p out
 	gcc -g -Wall -O1 -o out/d16 -DSTANDALONE=1 src/d16.c
 
+TEST_DEPS := out/Vtestbench out/a16 out/d16 tests/runtest
+
+TESTS := $(wildcard tests/*.s)
+
+RESULTS := $(patsubst %.s,out/%.s.status,$(TESTS))
+
+out/tests/%.s.status: tests/%.s $(TEST_DEPS)
+	@./tests/runtest $<
+
+test: $(RESULTS)
+	@echo ""
+	@echo TESTS FAILED: `grep FAIL out/tests/*.status | wc -l`
+	@echo TESTS PASSED: `grep PASS out/tests/*.status | wc -l`
+
 clean:
 	rm -rf out/
 
diff --git a/tests/000_load_registers.s b/tests/000_load_registers.s
@@ -0,0 +1,20 @@
+	mov r0, 0
+	mov r1, 1
+	mov r2, 0x1234
+	mov r3, -1
+	mov r4, -76
+
+	mov r15, 0
+	nop		; BUG should not be required
+	sw r0, [r15]
+	sw r1, [r15]
+	sw r2, [r15]
+	sw r3, [r15]
+	sw r4, [r15]
+	word 0xffff
+
+;0000 0000
+;0000 0001
+;0000 1234
+;0000 ffff
+;0000 ffb4
diff --git a/tests/001_simple_loop.s b/tests/001_simple_loop.s
@@ -0,0 +1,19 @@
+	mov r0, 5
+	mov r2, 0
+	mov r1, 17
+loop:
+	add r1, r1, r1
+	sub r0, r0, 1
+	add r2, r2, 1
+	bnz r0, loop
+
+	mov r15, 0
+	nop
+	sw r0, [r15]
+	sw r1, [r15]
+	sw r2, [r15]
+	word 0xffff
+
+;0000 0000
+;0000 0220
+;0000 0005
diff --git a/tests/runtest b/tests/runtest
@@ -0,0 +1,35 @@
+#!/bin/bash
+
+if [ ! -f "$1" ]; then
+	echo FAIL: No such file: $1
+	echo FAIL > "out/$1.status"
+	exit 0
+fi
+
+echo ""
+echo TEST: $1
+
+mkdir -p out/tests/
+
+if ! ./out/a16 "$1" "out/$1.hex" ; then
+	echo FAIL: $1 '(assmembly error)'
+	echo FAIL > "out/$1.status"
+	exit 0
+fi
+
+if ! ./out/Vtestbench -trace "out/$1.vcd" -load "out/$1.hex" | grep '^:WRI' > "out/$1.log" ; then
+	echo FAIL: Error simulating $1
+	echo FAIL > "out/$1.status"
+	exit 0
+fi
+
+grep '^;' "$1" | sed 's/;/:WRI /g' > "out/$1.tmpl"
+
+if ! diff "out/$1.tmpl" "out/$1.log" ; then
+	echo FAIL: $1 '(results differ)'
+	echo FAIL > "out/$1.status"
+	exit 0
+else
+	echo PASS: $1
+	echo PASS > "out/$1.status"
+fi