gateware

commit 48389018021f84e7cfbc4b3c6aad1b39ef184ece
parent 9999d68a84554065aa02743985f446f171a36098
Author: Brian Swetland <swetland@frotz.net>
Date:   Mon, 26 Nov 2018 18:43:59 -0800

cpu16: ensure registers use bram, fix lw/sw offsets

Diffstat:
M
hdl/cpu16.sv
 | 
48
+++++++++++++++++++++++++++++++++++++++++++++++-
A
tests/020-mem-write-offsets.s
 | 
20
++++++++++++++++++++

2 files changed, 67 insertions(+), 1 deletion(-)
diff --git a/hdl/cpu16.sv b/hdl/cpu16.sv
@@ -214,7 +214,7 @@ always_ff @(posedge clk) begin
 	ex_do_branch_zero <= do_branch_zero;
 	ex_do_mem_read = do_mem_read;
 	ex_do_mem_write = do_mem_write;
-	ex_imm <= (do_mem_read | do_mem_write) ? ir_imm_s7 : (do_use_imm9_or_imm6 ? ir_imm_s9 : ir_imm_s6);
+	ex_imm <= (do_mem_read | do_mem_write) ? ir_imm_s6 : (do_use_imm9_or_imm6 ? ir_imm_s9 : ir_imm_s6);
 end
 
 
@@ -258,6 +258,7 @@ module regs16(
 	output [15:0]bdata
 	);
 
+`ifdef verilator
 reg [15:0]rmem[0:7];
 reg [15:0]areg;
 reg [15:0]breg;
@@ -271,6 +272,51 @@ end
 
 assign adata = areg;
 assign bdata = breg;
+`else
+`ifdef YOSYS
+SB_RAM40_4K #(
+        .READ_MODE(0),
+        .WRITE_MODE(0)
+        )
+`else
+SB_RAM256x16
+`endif
+        bank_a (
+        .WADDR(wsel),
+        .RADDR(asel),
+        .MASK(16'b0),
+        .WDATA(wdata),
+        .RDATA(adata),
+        .WE(1'b1),
+        .WCLKE(wreg),
+        .WCLK(clk),
+        .RE(1'b1),
+        .RCLKE(1'b1),
+        .RCLK(clk)
+        );
+
+`ifdef YOSYS
+SB_RAM40_4K #(
+        .READ_MODE(0),
+        .WRITE_MODE(0)
+        )
+`else
+SB_RAM256x16
+`endif
+        bank_b (
+        .WADDR(wsel),
+        .RADDR(bsel),
+        .MASK(16'b0),
+        .WDATA(wdata),
+        .RDATA(bdata),
+        .WE(1'b1),
+        .WCLKE(wreg),
+        .WCLK(clk),
+        .RE(1'b1),
+        .RCLKE(1'b1),
+        .RCLK(clk)
+        );
+`endif
 
 endmodule
 
diff --git a/tests/020-mem-write-offsets.s b/tests/020-mem-write-offsets.s
@@ -0,0 +1,20 @@
+mov r0, 0
+mov r1, 0xff
+nop
+sw r1, [r0, 0x00]
+sw r1, [r0, 0x01]
+sw r1, [r0, 0x02]
+sw r1, [r0, 0x04]
+sw r1, [r0, 0x08]
+sw r1, [r0, 0x10]
+sw r0, [r1, -1]
+sw r1, [r1, -15]
+
+;0000 00ff
+;0001 00ff
+;0002 00ff
+;0004 00ff
+;0008 00ff
+;0010 00ff
+;00fe 0000
+;00f0 00ff