gateware

commit 4d03d6ad34b053c1fcbf419a2779771b9eb14c5a
parent 2adc3a08ca5798cd2aa5d86da78c0ceda8c02d89
Author: Brian Swetland <swetland@frotz.net>
Date:   Tue, 27 Nov 2018 20:16:42 -0800

cpu16: optional 64bit trace port

Diffstat:
M
hdl/cpu16.sv
 | 
27
+++++++++++++++++++++++++++

1 file changed, 27 insertions(+), 0 deletions(-)
diff --git a/hdl/cpu16.sv b/hdl/cpu16.sv
@@ -18,6 +18,10 @@ module cpu16(
 	input dat_rd_rdy,
 	input dat_wr_rdy,
 
+`ifdef CPU16_WITH_TRACE
+	output [63:0]trace,
+`endif
+
 	input reset
         );
 
@@ -198,6 +202,29 @@ reg ex_do_mem_write = 1'b0;
 
 reg [15:0]ex_imm = 16'b0;
 
+`ifdef CPU16_WITH_TRACE
+assign trace = {
+	pc,
+	ir,
+
+	ir_valid,
+	ir_ext_rdy,
+	ex_alu_op,
+	ex_wsel,
+
+	ex_do_wreg_alu,
+	ex_do_wreg_mem,
+	ex_do_adata_zero,
+	ex_do_bdata_imm,
+	ex_do_branch_imm,
+	ex_do_mem_read,
+	ex_do_mem_write,
+	ex_do_wr_link,
+
+	ex_imm
+	};
+`endif
+
 always_ff @(posedge clk) begin
 	// for mem-read or mem-write we use the ALU for Ra + imm7
 	ex_alu_op <= (do_adata_zero | do_mem_read | do_mem_write) ? 3'b0 : ir_alu_op;