commit 4fb8276d11d648b69cd75c91efb908fd5e868c0b
parent 1b432a91697a1399314f1bb554646178a2e7bb59
Author: Brian Swetland <swetland@frotz.net>
Date: Tue, 20 Nov 2018 12:26:43 -0800
vga: tidy up a bunch, fix synthesis in vivado
- use some systemverilog constructs
- stop using reg in parameters
- tweak the chardata state machine to fix synthesis in vivado
- this works in icecube2 and verilator too, but not yosys
- add an `ifdef YOSYS workaround for now
Diffstat:
5 files changed, 83 insertions(+), 58 deletions(-)
diff --git a/Makefile b/Makefile
@@ -37,7 +37,7 @@ out/ice40.lint: $(ICE40_SRCS)
out/ice40.ys: $(ICE40_SRCS) Makefile
@mkdir -p out
@echo generating $@
- @echo verilog_defines -DHEX_PATHS > $@
+ @echo verilog_defines -DHEX_PATHS -DYOSYS > $@
@for src in $(ICE40_SRCS) ; do echo read_verilog -sv $$src ; done >> $@
@echo synth_ice40 -top top -blif out/ice40.blif -json out/ice40.json >> $@
diff --git a/hdl/vga/chardata.v b/hdl/vga/chardata.v
@@ -17,7 +17,7 @@ module pixeldata(
input advance,
input [7:0] line,
- output reg [11:0] pixel,
+ output [11:0] pixel,
input [7:0] vram_data,
output [10:0] vram_addr
@@ -31,9 +31,9 @@ chardata chardata(
.newline(newline),
.line(line),
.next(next),
- .cdata(new_cdata),
+ .cdata_o(new_cdata),
.vram_data(vram_data),
- .vram_addr(vram_addr)
+ .vram_addr_o(vram_addr)
);
reg [7:0] cdata, next_cdata;
@@ -72,9 +72,10 @@ always @(*) begin
next_bitcount = 4'hF;
end
- pixel = (cdata[bitcount[3:1]] ? 12'hFFF : 12'h00F);
end
+assign pixel = (cdata[bitcount[3:1]] ? 12'hFFF : 12'h00F);
+
always @(posedge clk) begin
bitcount <= next_bitcount;
state <= next_state;
@@ -89,10 +90,10 @@ module chardata(
input newline,
input next,
input [7:0] line,
- output reg [7:0] cdata,
+ output [7:0] cdata_o,
input [7:0] vram_data,
- output reg [10:0] vram_addr
+ output [10:0] vram_addr_o
);
`define SWAIT 2'h0
@@ -106,13 +107,19 @@ reg [1:0] state = `SWAIT, next_state;
reg [10:0] next_addr;
reg [7:0] next_cdata;
+reg [7:0] cdata;
+reg [10:0] vram_addr;
+
+assign cdata_o = cdata;
+assign vram_addr_o = vram_addr;
+
`ifdef HEX_PATHS
initial $readmemh("hdl/vga/prom.txt", pattern_rom);
`else
initial $readmemh("prom.txt", pattern_rom);
`endif
-always @(*) begin
+always_comb begin
next_state = state;
next_addr = vram_addr;
next_cdata = cdata;
@@ -122,6 +129,9 @@ always @(*) begin
next_addr = { line[7:3], 6'b0 };
next_pline = line[2:0];
end
+`ifndef YOSYS
+ else
+`endif
case (state)
`SWAIT: if (next) begin
next_state = `SLOAD;
@@ -140,7 +150,7 @@ always @(*) begin
endcase
end
-always @(posedge clk) begin
+always_ff @(posedge clk) begin
state <= next_state;
vram_addr <= next_addr;
cdata <= next_cdata;
diff --git a/hdl/vga/vga.v b/hdl/vga/vga.v
@@ -9,29 +9,53 @@
module vga(
input clk,
- output reg hs,
- output reg vs,
- output reg [3:0] r,
- output reg [3:0] g,
- output reg [3:0] b,
-
- output reg newline,
- output reg advance,
- output reg [7:0] line,
+ output hs,
+ output vs,
+ output [3:0] r,
+ output [3:0] g,
+ output [3:0] b,
+
+ output newline,
+ output advance,
+ output [7:0] line,
input [11:0] pixel
);
-reg [9:0] hcount;
-reg [9:0] vcount;
+reg hsync;
+reg vsync;
+reg active;
+reg startline;
+reg [9:0] hcount = 10'b0;
+reg [9:0] vcount = 10'b0;
+reg next_hsync;
+reg next_vsync;
+reg next_active;
+reg next_startline;
reg [9:0] next_hcount;
reg [9:0] next_vcount;
-reg next_hs, next_vs;
-reg active;
-reg next_startline;
-reg [9:0] next_line;
+reg [9:0] next_lineno;
+reg [7:0] lineno;
+
+assign hs = hsync;
+assign vs = vsync;
+assign line = lineno;
+assign advance = active;
+assign newline = startline;
+
+assign r = active ? pixel[11:8] : 4'd0;
+assign g = active ? pixel[7:4] : 4'd0;
+assign b = active ? pixel[3:0] : 4'd0;
+
+always_comb begin
+ next_hsync = 1'b0;
+ next_vsync = 1'b0;
+ next_hcount = 10'd0;
+ next_vcount = 10'd0;
+ next_active = 1'b0;
+ next_startline = 1'b0;
+ next_lineno = 10'b0;
-always @* begin
if (hcount == 10'd799) begin
if (vcount == 10'd523)
next_vcount = 10'd0;
@@ -49,43 +73,32 @@ always @* begin
next_startline = 1'b0;
if (next_hcount < 10'd96)
- next_hs = 1'b0;
+ next_hsync = 1'b0;
else
- next_hs = 1'b1;
+ next_hsync = 1'b1;
if (next_vcount < 10'd2)
- next_vs = 1'b0;
+ next_vsync = 1'b0;
else
- next_vs = 1'b1;
+ next_vsync = 1'b1;
- active = 1'b0;
if ((next_vcount > 31) && (next_vcount < 512))
if ((next_hcount > 143) && (next_hcount < 784))
- active = 1'b1;
+ next_active = 1'b1;
- next_line = next_vcount - 10'd32;
+ next_lineno = next_vcount - 10'd32;
end
-always @(posedge clk) begin
+always_ff @(posedge clk) begin
hcount <= next_hcount;
vcount <= next_vcount;
- hs <= next_hs;
- vs <= next_vs;
+ hsync <= next_hsync;
+ vsync <= next_vsync;
/* signals to pixel generator */
- newline <= next_startline;
- advance <= active;
- line <= next_line[8:1];
-
- if (active) begin
- r <= pixel[11:8];
- g <= pixel[7:4];
- b <= pixel[3:0];
- end else begin
- r <= 4'd0;
- g <= 4'd0;
- b <= 4'd0;
- end
+ startline <= next_startline;
+ active <= next_active;
+ lineno <= next_lineno[8:1];
end
endmodule
diff --git a/hdl/vga/vga40x30x2.v b/hdl/vga/vga40x30x2.v
@@ -52,15 +52,14 @@ pixeldata pixeldata0(
);
videoram #(8,11) vram(
- .rclk(clk25m),
+ .rclk(clk25m),
.re(1'b1),
- .rdata(vram_rdata),
- .raddr(vram_raddr),
+ .rdata(vram_rdata),
+ .raddr(vram_raddr),
.wclk(vram_clk),
- .we(vram_we),
- .wdata(vram_wdata[7:0]),
- .waddr(vram_waddr[10:0])
- );
-
+ .we(vram_we),
+ .wdata(vram_wdata[7:0]),
+ .waddr(vram_waddr[10:0])
+ );
endmodule
diff --git a/hdl/vga/videoram.v b/hdl/vga/videoram.v
@@ -10,10 +10,13 @@ module videoram #(parameter DWIDTH=16, parameter AWIDTH=8) (
input [DWIDTH-1:0] wdata,
input rclk, input re,
input [AWIDTH-1:0] raddr,
- output reg [DWIDTH-1:0] rdata
+ output [DWIDTH-1:0] rdata
);
reg [DWIDTH-1:0] mem[0:2**AWIDTH-1];
+reg [DWIDTH-1:0] data;
+
+assign rdata = data;
`ifdef HEX_PATHS
initial $readmemh("hdl/vga/vram.txt", mem);
@@ -28,7 +31,7 @@ end
always @(posedge rclk) begin
if (re)
- rdata <= mem[raddr];
+ data <= mem[raddr];
end
endmodule
