gateware

commit 555b78efa9093a04f1fd261af60f244bda1d2249
parent 0d6544e47a7bf4f517653ba281efa9f296f672b2
Author: Brian Swetland <swetland@frotz.net>
Date:   Sun, 18 Nov 2018 11:32:14 -0800

build fixes

- handle relative or absolute paths for readmemh() via HEX_PATHS define
- generate script file to drive yosys for better control and ability
  to tweak defines
- actually generate out/ice40.lint

Diffstat:
M
Makefile
 | 
12
++++++++++--
M
hdl/vga/chardata.v
 | 
4
++++
M
hdl/vga/videoram.v
 | 
4
++++

3 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/Makefile b/Makefile
@@ -29,10 +29,18 @@ out/ice40.bin: out/ice40.asc
 out/ice40.lint: $(ICE40_SRCS)
 	@mkdir -p out
 	$(VERILATOR) --top-module top --lint-only $(ICE40_SRCS)
+	@touch out/ice40.lint
 
-out/ice40.blif: $(ICE40_SRCS) out/ice40.lint
+out/ice40.ys: $(ICE40_SRCS)
 	@mkdir -p out
-	$(YOSYS) -p 'synth_ice40 -top top -blif out/ice40.blif' $(ICE40_SRCS) 2>&1 | tee out/ice40.synth.log
+	@echo generating $@
+	@echo verilog_defines -DHEX_PATHS > $@
+	@for src in $(ICE40_SRCS) ; do echo read_verilog $$src ; done >> $@
+	@echo synth_ice40 -top top -blif out/ice40.blif >> $@
+
+out/ice40.blif: out/ice40.ys out/ice40.lint
+	@mkdir -p out
+	$(YOSYS) -s out/ice40.ys 2>&1 | tee out/ice40.synth.log
 
 out/ice40.asc: out/ice40.blif
 	@mkdir -p out
diff --git a/hdl/vga/chardata.v b/hdl/vga/chardata.v
@@ -106,7 +106,11 @@ reg [1:0] state = `SWAIT, next_state;
 reg [10:0] next_addr;
 reg [7:0] next_cdata;
 
+`ifdef HEX_PATHS
+initial $readmemh("hdl/vga/prom.txt", pattern_rom);
+`else
 initial $readmemh("prom.txt", pattern_rom);
+`endif
 
 always @(*) begin
 	next_state = state;
diff --git a/hdl/vga/videoram.v b/hdl/vga/videoram.v
@@ -15,7 +15,11 @@ module videoram #(parameter DWIDTH=16, parameter AWIDTH=8) (
 
 reg [DWIDTH-1:0] mem[0:2**AWIDTH-1];
 
+`ifdef HEX_PATHS
+initial $readmemh("hdl/vga/vram.txt", mem);
+`else
 initial $readmemh("vram.txt", mem);
+`endif
 
 always @(posedge wclk) begin
 	if (we)