commit c9583916905378daf05e700b211454b3a942757d
parent 8caf74ca1c7a04da4e0d0225ec6e313e89d68ddb
Author: Brian Swetland <swetland@frotz.net>
Date: Sat, 24 Nov 2018 22:44:51 -0800
tests: update for cpu16v4
- start on some new basic tests
- exercise mov, alu, and extended mov and alu ops
- illustrate data hazards (fails)
- test runner now supports tests that declare the intended state of
the register set as well as write ops
Diffstat:
12 files changed, 134 insertions(+), 100 deletions(-)
diff --git a/tests/000-load-registers.s b/tests/000-load-registers.s
@@ -1,20 +0,0 @@
- mov r0, 0
- mov r1, 1
- mov r2, 0x1234
- mov r3, -1
- mov r4, -76
-
- mov r15, 0
- nop ; BUG should not be required
- sw r0, [r15]
- sw r1, [r15]
- sw r2, [r15]
- sw r3, [r15]
- sw r4, [r15]
- word 0xffff
-
-;0000 0000
-;0000 0001
-;0000 1234
-;0000 ffff
-;0000 ffb4
diff --git a/tests/000-mov-imm.s b/tests/000-mov-imm.s
@@ -0,0 +1,21 @@
+mov r0, 0x10
+mov r1, 0x20
+mov r2, 0x30
+mov r3, 0x40
+mov r4, 0x50
+mov r5, 0x60
+mov r6, 0x70
+mov r7, 0x80
+
+nop
+halt
+
+;R0 0010
+;R1 0020
+;R2 0030
+;R3 0040
+;R4 0050
+;R5 0060
+;R6 0070
+;R7 0080
+
diff --git a/tests/001-mov-imm-bits.s b/tests/001-mov-imm-bits.s
@@ -0,0 +1,20 @@
+mov r0, 0x01
+mov r1, 0x02
+mov r2, 0x04
+mov r3, 0x08
+mov r4, 0x10
+mov r5, 0x20
+mov r6, 0x40
+mov r7, -256
+nop
+halt
+
+;R0 0001
+;R1 0002
+;R2 0004
+;R3 0008
+;R4 0010
+;R5 0020
+;R6 0040
+;R7 ff00
+
diff --git a/tests/001-simple-loop.s b/tests/001-simple-loop.s
@@ -1,19 +0,0 @@
- mov r0, 5
- mov r2, 0
- mov r1, 17
-loop:
- add r1, r1, r1
- sub r0, r0, 1
- add r2, r2, 1
- bnz r0, loop
-
- mov r15, 0
- nop
- sw r0, [r15]
- sw r1, [r15]
- sw r2, [r15]
- word 0xffff
-
-;0000 0000
-;0000 0220
-;0000 0005
diff --git a/tests/002-alu-ops-1.s b/tests/002-alu-ops-1.s
@@ -0,0 +1,20 @@
+mov r0, 0x11
+mov r1, 0x22
+mov r2, 0x33
+mov r3, 0x44
+add r4, r1, r2
+sub r5, r3, r1
+orr r6, r1, r3
+sge r7, r3, r2
+
+nop
+halt
+
+;R0 0011
+;R1 0022
+;R2 0033
+;R3 0044
+;R4 0055
+;R5 0022
+;R6 0066
+;R7 0001
diff --git a/tests/002-simple-math.s b/tests/002-simple-math.s
@@ -1,21 +0,0 @@
- mov r0, 0
- add r1, r0, 1
- add r2, r0, 2
- add r3, r1, 1
- add r4, r3, 1
-
- mov r15, 0
- nop
-
- sw r0, [r15]
- sw r1, [r15]
- sw r2, [r15]
- sw r3, [r15]
- sw r4, [r15]
- word 0xffff
-
-;0000 0000
-;0000 0001
-;0000 0002
-;0000 0002
-;0000 0003
diff --git a/tests/003-increment.s b/tests/003-increment.s
@@ -1,13 +0,0 @@
- mov r0, 0
- add r0, r0, 1
- add r0, r0, 1
- add r0, r0, 1
- add r0, r0, 1
-
- mov r15, 0
- nop
-
- sw r0, [r15]
- word 0xffff
-
-;0000 0004
diff --git a/tests/003-mov-imm-ext.s b/tests/003-mov-imm-ext.s
@@ -0,0 +1,21 @@
+mov r0, 0x1234
+mov r1, 0xA7A7
+mov r2, 0x1111
+mov r3, 0x2222
+mov r4, 0x4444
+mov r5, 0x8888
+mov r6, 0x5A5A
+mov r7, 0x8080
+
+nop
+halt
+
+;R0 1234
+;R1 a7a7
+;R2 1111
+;R3 2222
+;R4 4444
+;R5 8888
+;R6 5a5a
+;R7 8080
+
diff --git a/tests/004-alu-ops-ext.s b/tests/004-alu-ops-ext.s
@@ -0,0 +1,21 @@
+mov r0, 0
+mov r1, 0x7777
+add r2, r0, 0x1234
+and r3, r1, 0xF1F1
+sub r4, r1, 0x1111
+slt r5, r1, 0x8000
+sge r6, r1, 0x8000
+sge r7, r1, 0x7777
+
+nop
+halt
+
+;R0 0000
+;R1 7777
+;R2 1234
+;R3 7171
+;R4 6666
+;R5 0001
+;R6 0000
+;R7 0001
+
diff --git a/tests/004-write-loop.s b/tests/004-write-loop.s
@@ -1,25 +0,0 @@
- mov r15, 0x100
- mov r14, 0x108
- mov r0, 0xabcd
-
-loop:
- slt r1, r15, r14
- bnz r1, done
- sw r0, [r15]
- add r15, r15, 1
- nop
- b loop
-
-done:
- word 0xffff
-
-
-;0100 abcd
-;0101 abcd
-;0102 abcd
-;0103 abcd
-;0104 abcd
-;0105 abcd
-;0106 abcd
-;0107 abcd
-;0100 0000
diff --git a/tests/100-hazards-1.s b/tests/100-hazards-1.s
@@ -0,0 +1,21 @@
+mov r0, 0xff
+nop
+mov r1, r0
+mov r2, r1
+mov r3, r2
+mov r4, r3
+mov r5, r4
+mov r6, r5
+mov r7, r6
+
+nop
+halt
+
+;R0 00ff
+;R1 00ff
+;R2 00ff
+;R3 00ff
+;R4 00ff
+;R5 00ff
+;R6 00ff
+;R7 00ff
diff --git a/tests/runtest b/tests/runtest
@@ -17,13 +17,21 @@ if ! ./out/a16 "$1" "out/$1.hex" ; then
exit 0
fi
-if ! ./out/cpu/Vtestbench -trace "out/$1.vcd" -load "out/$1.hex" | grep '^:WRI' > "out/$1.log" ; then
+if ! ./out/cpu/Vtestbench -trace "out/$1.vcd" -load "out/$1.hex" > "out/$1.raw" ; then
echo FAIL: Error simulating $1
echo FAIL > "out/$1.status"
exit 0
fi
-grep '^;' "$1" | sed 's/;/:WRI /g' > "out/$1.tmpl"
+# extract WRItes from log and test
+grep '^:WRI' "out/$1.raw" > "out/$1.log"
+grep '^;[0-9a-fA-F]' "$1" | sed 's/;/:WRI /g' > "out/$1.tmpl"
+
+# extract REGister state from log and test (if test includes them)
+if grep -q '^;R' "$1" ; then
+ grep '^:REG' "out/$1.raw" >> "out/$1.log"
+ grep '^;R' "$1" | sed 's/;/:REG /g' >> "out/$1.tmpl"
+fi
if ! diff "out/$1.tmpl" "out/$1.log" ; then
echo FAIL: $1 '(results differ)'
