gateware

commit e250a1aaa851485022cabacd1e3366119660f917
parent b8a73ab3f7e443e1a9816cfd07af331fd475faec
Author: Brian Swetland <swetland@frotz.net>
Date:   Tue, 29 Dec 2015 20:37:46 -0800

Tweak verilator driver to have the first +clk at 10ns

This lines the clock cycles up with gtkwave's 10ns default grid.

Diffstat:
M
src/testbench.cpp
 | 
8
++++++++

1 file changed, 8 insertions(+), 0 deletions(-)
diff --git a/src/testbench.cpp b/src/testbench.cpp
@@ -137,6 +137,14 @@ int main(int argc, char **argv) {
 	tfp->open(vcdname);
 #endif
 
+// first tick, line up with gtk's vert lines
+	testbench->eval();
+#ifdef TRACE
+	tfp->dump(now);
+	now += 10;
+#endif
+	testbench->clk = !testbench->clk;
+
 	while (!Verilated::gotFinish()) {
 		testbench->eval();
 #ifdef TRACE