gateware

commit f53383092995c13956a5e067bbc486f2df7138d2
parent 48ec3cbb1ee445488f2e0f2192050afa2d229d83
Author: Brian Swetland <swetland@frotz.net>
Date:   Wed, 22 Jan 2020 16:21:17 -0800

new readme

Diffstat:
A
README
 | 
16
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1 file changed, 16 insertions(+), 0 deletions(-)
diff --git a/README b/README
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+
+This is a collection of little open source FPGA hobby projects
+--------------------------------------------------------------
+
+The build system can target nextpnr-ice40, nextpnr-ecp5, (Lattice
+ICE40 and ECP5 family parts), verilator (simulation), and vivado
+(Xilinx parts).
+
+Projects are defined in project/*.def and all buildable projects
+can be listed with "make" and built with "make <projectname>" or
+"make all"
+
+Final build products are deposited in out/... and intermediate
+build products, logs, and so on, in out/-nextpnr-/{projectname}/...,
+out/-vsim-/{projectname}/..., etc.
+