commit fbec7fe80c98a353c6bd4c74a572ca9f43cde0ec
parent 9711988d04a02766ed8b339c1dda6b424ce8213e
Author: Brian Swetland <swetland@frotz.net>
Date: Tue, 29 Dec 2015 22:51:01 -0800
update ISA document
Diffstat:
| M | hdl/cpu/isa.txt | | | 77 | +++++++++++++++++++++++++++++++++++++++++------------------------------------ |
1 file changed, 41 insertions(+), 36 deletions(-)
diff --git a/hdl/cpu/isa.txt b/hdl/cpu/isa.txt
@@ -1,24 +1,24 @@
-basic instruction set
----------------------
-iiii iiii aaaa 0000 mov Ra, s8
-iiii iiii aaaa 0001 mhi Ra, s8
-ffff bbbb aaaa 0010 alu Ra, Ra, Rb
-iiii ffff aaaa 0011 alu Ra, Ra, s4
-ffff bbbb aaaa 01cc alu Rc, Ra, Rb
-iiii bbbb aaaa 1000 lw Ra, [Rb, si4]
-iiii bbbb aaaa 1001 sw Ra, [Rb, si4]
-iiii iiii aaaa 1010 bnz Ra, rel8
-iiii iiii aaaa 1011 bz Ra, rel8
-iiii iiii iiii 1100 b rel12
-iiii iiii iiii 1101 bl rel12
-0000 bbbb xxxx 1110 b Rb
-0001 bbbb xxxx 1110 bl Rb
+Basic Instructions Assembly Syntax Operation
+--------------------- -------------------- -----------------------------
+iiii iiii aaaa 0000 mov Ra, si8 Ra = si8
+iiii iiii aaaa 0001 mhi Ra, si8 Ra = (Ra & 0xFF) | (si8 << 8)
+ffff bbbb aaaa 0010 alu Ra, Ra, Rb Ra = Ra <fn> Rb
+iiii ffff aaaa 0011 alu Ra, Ra, si4 Ra = Ra <fn> si4
+ffff bbbb aaaa 01cc alu Rc, Ra, Rb Rc = Ra <fn> Rb
+iiii bbbb aaaa 1000 lw Ra, [Rb, si4] Ra = [Rb + si4]
+iiii bbbb aaaa 1001 sw Ra, [Rb, si4] [Rb + si4] = Ra
+iiii iiii aaaa 1010 bnz Ra, si8 if (Ra != 0) PC += si8
+iiii iiii aaaa 1011 bz Ra, si8 if (Ra == 0) PC += si8
+iiii iiii iiii 1100 b si12 PC += si12
+iiii iiii iiii 1101 bl si12 R14 = PC, PC += si12,
+0000 bbbb xxxx 1110 b Rb PC = Rb
+0001 bbbb xxxx 1110 bl Rb R14 = PC, PC = Rb
0010 xxxx xxxx 1110 nop
-extended instruction set
-------------------------
-0011 xxxx xxxx 1110 iret
+Extended Instructions <--- Not implemented yet.
+--------------------- Will likely change during
+0011 xxxx xxxx 1110 iret implementation.
0100 nnnn aaaa 1110 mov Ra, Sn
0101 nnnn aaaa 1110 mov Sn, Ra
0110 aaaa bbbb 1110 mov Ra', Rb
@@ -32,18 +32,18 @@ xxxx xxxx 0011 1111 undefined
xxxx xxxx 01xx 1111 undefined
xxxx xxxx 1xxx 1111 undefined
-alu opcodes
------------
-0000 mov r = b
-0001 and r = a & b
-0010 orr r = a | b
-0011 xor r = a ^ b
-0100 add r = a + b
-0101 sub r = a - b
-0110 mul r = a * b
-0111 mhi r = (b << 8) | (a & 0xFF)
-1000 slt r = a < b
-1001 sle r = a <= b
+ALU Functions (<fn>) Key
+-------------------------------------- ----------------------------------
+0000 mov r = b si4 signed 4bit immediate
+0001 and r = a & b si8 signed 8bit immediate
+0010 orr r = a | b si12 signed 12bit immediate
+0011 xor r = a ^ b fn ALU function
+0100 add r = a + b R0-R15 general purpose registers
+0101 sub r = a - b PC program counter
+0110 mul r = a * b
+0111 mhi r = (b << 8) | (a & 0xFF) S0-S15 system control registers
+1000 slt r = a < b F0-F7 system flag bits
+1001 sle r = a <= b R0'-R15' banked registers
1010 shr r = a >> 1
1011 shl r = a << 1
1100 bis r = a | (1 << b[3:0])
@@ -51,10 +51,15 @@ alu opcodes
1110 tbs r = a & (1 << b[3:0])
1111 bit r = 1 << b[3:0]
-r0 - r12 general use
-r13 stack (by convention only)
-r14 link register (for BL ops)
-r15 scratch (for assembler use)
-s0 - s15 system registers
-f0 - f7 system flags
+Register Usage / Procedure Call Standard
+-----------------------------------------
+R0 - R3 parameters & results
+R4 - R11 caller save, working variables
+R12 reserved for OS/runtime global use
+R13 stack pointer
+R14 link register* (for branch-and-link)
+R15 scratch (for assembler/linker use)
+* The processor can *only* save PC to R14 on BL calls.
+ All other register assignements are merely to simplify
+ software interworking, not required by the architecture.
