jtagonizer

commit 390f574f27d029d00f7f500941cd7ae30780b62a
parent c998fef594732fd55cd8d5517162804486951cef
Author: Brian Swetland <swetland@frotz.net>
Date:   Fri, 10 Oct 2014 09:40:29 -0700

zynq: fold fpga tool into zynq tool

It probably needs a better name since it can deal with bitfile
downloads to any 7-series fpga.

Diffstat:
M
Makefile
 | 
11
+++--------
M
fpga.c
 | 
49
++++++++++++++++++++++++++++++-------------------
M
zynq.c
 | 
17
++++++++++++++++-

3 files changed, 49 insertions(+), 28 deletions(-)
diff --git a/Makefile b/Makefile
@@ -3,7 +3,7 @@ CFLAGS := -Wall -O0 -g
 
 LIBS := -lusb-1.0 -lrt
 
-all: zynq fpga debug mem
+all: zynq debug mem
 
 JTAG_OBJS := jtag-mpsse-driver.o jtag-core.o jtag.o
 $(JTAG_OBJS): jtag.h jtag-driver.h
@@ -15,16 +15,11 @@ $(DAP_OBJS): jtag.h jtag-driver.h dap.h dap-registers.h
 dap-test: $(DAP_OBJS)
 	$(CC) -o dap-test $(DAP_OBJS) $(LIBS)
 
-ZYNQ_OBJS := zynq.o v7debug.o dap.o jtag-core.o jtag-mpsse-driver.o
+ZYNQ_OBJS := zynq.o fpga.o v7debug.o dap.o jtag-core.o jtag-mpsse-driver.o
 $(ZYNQ_OBJS): jtag.h jtag-driver.h dap.h dap-registers.h v7debug.h v7debug-registers.h
 zynq: $(ZYNQ_OBJS)
 	$(CC) -o zynq $(ZYNQ_OBJS) $(LIBS)
 
-FPGA_OBJS := fpga.o jtag-core.o jtag-mpsse-driver.o
-$(FPGA_OBJS): jtag.h jtag-driver.h
-fpga: $(FPGA_OBJS)
-	$(CC) -o fpga $(FPGA_OBJS) $(LIBS)
-
 DEBUG_OBJS := debug.o jtag-core.o jtag-mpsse-driver.o
 $(DEBUG_OBJS): jtag.h jtag-driver.h
 debug: $(DEBUG_OBJS)
@@ -36,4 +31,4 @@ mem: $(MEM_OBJS)
 	$(CC) -o mem $(MEM_OBJS) $(LIBS)
 
 clean:
-	rm -f *.o jtag dap-test zynq fpga debug mem
+	rm -f *.o jtag dap-test zynq debug mem
diff --git a/fpga.c b/fpga.c
@@ -95,6 +95,7 @@
 #define STAT_STATE(n)	(((n) >> 18) & 7)
 #define STAT_MODE(n)	(((n) >> 8) & 7)
 
+#if 0
 static void *loadfile(const char *fn, u32 *sz) {
 	int fd;
 	off_t end;
@@ -113,6 +114,7 @@ oops:
 	close(fd);
 	return NULL;
 }
+#endif
 
 static u8 bitrev(u8 x) {
 	x = (x << 4) | (x >> 4);
@@ -193,22 +195,9 @@ static int fpga_warm_boot(JTAG *jtag) {
 #endif
 }
 
-int main(int argc, char **argv) {
-	JTAG *jtag;
-	u8 *data = NULL;
-	u32 sz, n;
-
-	if (argc == 2) {
-		if ((data = loadfile(argv[1], &sz)) == NULL) {
-			fprintf(stderr, "error: cannot load '%s'\n", argv[1]);
-			return -1;
-		}
-		for (n = 0; n < sz; n++) {
-			data[n] = bitrev(data[n]);
-		}
-	}
+int fpga_send_bitfile(JTAG *jtag, void *data, u32 sz) {
+	u32 n;
 
-	if (jtag_mpsse_open(&jtag)) return -1;
 	if (jtag_enumerate(jtag) < 0) return -1;
 	if (jtag_select_by_family(jtag, "Xilinx 7")) return -1;
 
@@ -232,7 +221,7 @@ int main(int argc, char **argv) {
 	}
 	fprintf(stderr, "status: %08x S%d\n", n, STAT_STATE(n));
 
-	fprintf(stderr, "downloading...\n");
+	fprintf(stderr, "fpga: downloading...\n");
 	jtag_goto(jtag, JTAG_RESET);
 	n = IR_CFG_IN;
 	jtag_ir_wr(jtag, IR_LEN, &n);
@@ -254,9 +243,31 @@ int main(int argc, char **argv) {
 		return -1;
 	}
 	if (n & STAT_INIT_COMPLETE) {
-		fprintf(stderr, "init complete\n");
+		fprintf(stderr, "fpga: init complete\n");
+		return 0;
 	}
-
-	return 0;
+	return -1;
 }
 
+#if 0
+int main(int argc, char **argv) {
+	JTAG *jtag;
+	u8 *data = NULL;
+	u32 sz, n;
+
+	if (argc == 2) {
+		if ((data = loadfile(argv[1], &sz)) == NULL) {
+			fprintf(stderr, "error: cannot load '%s'\n", argv[1]);
+			return -1;
+		}
+		for (n = 0; n < sz; n++) {
+			data[n] = bitrev(data[n]);
+		}
+	}
+
+	if (jtag_mpsse_open(&jtag)) return -1;
+	if (jtag_enumerate(jtag) < 0) return -1;
+
+	return fpga_send_bitfile(jtag, data, sz);
+}
+#endif
diff --git a/zynq.c b/zynq.c
@@ -49,11 +49,15 @@ int usage(void) {
 	fprintf(stderr,
 "zynq run <image>              download image to 0, resume cpu0 at 0\n"
 "zynq regs                     pause both cpus, dump registers, resume\n"
+"zynq reset                    reset the SoC\n"
+"zynq fpga <bitfile>           reset fpga and download bitfile to it\n"
 "\n"
 		);
 	return -1;
 }
 
+int fpga_send_bitfile(JTAG *jtag, void *data, u32 sz);
+
 int main(int argc, char **argv) {
 	JTAG *jtag;
 	DAP *dap;
@@ -67,6 +71,18 @@ int main(int argc, char **argv) {
 	}
 
 	if (jtag_mpsse_open(&jtag)) return -1;
+
+	if (!strcmp(argv[1], "fpga")) {
+		if (argc != 3) {
+			return usage();
+		}
+		if ((data = loadfile(argv[2], &sz)) == NULL) {
+			fprintf(stderr, "error: could not load '%s'\n", argv[2]);
+			return -1;
+		}
+		return fpga_send_bitfile(jtag, data, sz);
+	}
+
 	if ((dap = dap_init(jtag, 0x4ba00477)) == NULL) return -1;
 	if (dap_attach(dap)) return -1;
 	if ((d0 = debug_init(dap, ZYNQ_DEBUG0_APN, ZYNQ_DEBUG0_BASE)) == NULL) return -1;
@@ -98,7 +114,6 @@ int main(int argc, char **argv) {
 		debug_detach(d0);
 		debug_detach(d1);
 	} else if (!strcmp(argv[1], "reset")) {
-		u32 x;
 		dap_mem_wr32(dap, 0, 0xF8000008, 0xDF0D);
 		dap_mem_wr32(dap, 0, 0xF8000200, 1);
 	} else {