commit 9d593b6becb3f017b5df2e14e2e79a41d2fb02a7 parent 66b6e2a37d9700a1c985389a3821cee7b7ec702b Author: Brian Swetland <swetland@frotz.net> Date: Wed, 23 Oct 2019 02:33:48 -0700 rvsim: fence and fence.i (nop) - no complex memory model here Diffstat:
| M | riscv.h | | | 4 | ++++ |
| M | rvsim.c | | | 9 | +++++++-- |
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/riscv.h b/riscv.h @@ -112,6 +112,10 @@ static inline uint32_t get_iC(uint32_t ins) { #define F3_CSRRS 0b10 #define F3_CSRRC 0b11 +// further discrimination of OC_MISC_MEM (14:12) +#define F3_FENCE 0b000 +#define F3_FENCE_I 0b001 + // CSR values #define CSR_MVENDORID 0xF11 #define CSR_MARCHID 0xF12 diff --git a/rvsim.c b/rvsim.c @@ -173,8 +173,13 @@ void rvsim(rvstate_t* s) { case OC_CUSTOM_0: goto inval; case OC_MISC_MEM: - if (get_fn3(ins) != 0) goto inval; - // fence -- do nothing + switch (get_fn3(ins)) { + case F3_FENCE: + case F3_FENCE_I: + break; + default: + goto inval; + } break; case OC_OP_IMM: { uint32_t a = RdR1();