xdebug

commit 2e9320d1df9bb1947311cd9aad517719fd724431
parent e2956ea711ef5b81f12ceaa51e945669bda97831
Author: Brian Swetland <swetland@frotz.net>
Date:   Fri,  3 Mar 2023 02:28:32 -0800

transport; add clock freq control

Diffstat:
M
src/arm-debug.h
 | 
1
+
M
src/cmsis-dap-protocol.h
 | 
3
+++
M
src/transport.c
 | 
8
+++++++-
M
src/transport.h
 | 
2
++

4 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/src/arm-debug.h b/src/arm-debug.h
@@ -25,6 +25,7 @@
 #define DP_ABORT_STKERRCLR        0x04U // clear CS.STICKYERR
 #define DP_ABORT_WDERRCLR         0x08U // clear CS.WDATAERR
 #define DP_ABORT_ORUNERRCLR       0x10U // clear CS.STICKYORUN
+#define DP_ABORT_ALLCLR           0x1EU
 
 #define DP_CS_ORUNDETECT          0x00000001U // RW
 #define DP_CS_STICKYORUN          0x00000002U // RO/WI
diff --git a/src/cmsis-dap-protocol.h b/src/cmsis-dap-protocol.h
@@ -61,6 +61,9 @@
 // Response BYTE(Status) BYTE(Execute)
 // Execute 1 = device specific reset sequence implemented
 
+#define DAP_SWJ_Clock 0x11 // WORD(hz)
+// Response BYTE(Status)
+
 #define DAP_SWJ_Pins 0x10 // BYTE(PinOut) BYTE(PinSel) WORD(PinWaitMicros)
 // Response BYTE(PinInput)
 // Modify pins (PinOut) where selected (PinSel)
diff --git a/src/transport.c b/src/transport.c
@@ -137,6 +137,12 @@ int dap_swd_configure(DC* dc, unsigned cfg) {
 	return dap_cmd_std(dc, "dap_swd_configure()", io, 2, 2);
 }
 
+int dc_set_clock(DC* dc, uint32_t hz) {
+	uint8_t io[5] = { DAP_SWJ_Clock,
+		hz, hz >> 8, hz >> 16, hz >> 24 };
+	return dap_cmd_std(dc, "dap_swj_clock()", io, 5, 2);
+}
+
 static int dap_xfer_config(DC* dc, unsigned idle, unsigned wait, unsigned match) {
 	// clamp to allowed max values
 	if (idle > 255) idle = 255;
@@ -550,7 +556,7 @@ static int dap_configure(DC* dc) {
 
 	dap_connect(dc);
 	dap_swd_configure(dc, CFG_Turnaround_1);
-	dap_xfer_config(dc, 8, 64, 0);
+	dap_xfer_config(dc, 8, 64, 64);
 	return DC_OK;
 }
 
diff --git a/src/transport.h b/src/transport.h
@@ -7,6 +7,8 @@
 
 typedef struct debug_context dctx_t;
 
+int dc_set_clock(dctx_t* dc, uint32_t hz);
+
 // queue Debug Port reads and writes
 // DP.SELECT will be updated as necessary
 void dc_q_dp_rd(dctx_t* dc, unsigned dpaddr, uint32_t* val);