zynq-sandbox

commit a8c9ea29a446ff7400552b775219ac7f524fb97c
parent 4ff0fa1fa098b01c187ff775fad1749e54098998
Author: Brian Swetland <swetland@frotz.net>
Date:   Tue,  8 Jul 2014 18:07:47 -0700

axi_registers: properly assert RLAST on data read cycle

Diffstat:
M
hdl/axi_registers.sv
 | 
5
+++++

1 file changed, 5 insertions(+), 0 deletions(-)
diff --git a/hdl/axi_registers.sv b/hdl/axi_registers.sv
@@ -110,6 +110,7 @@ rstate_t rstate_next;
 
 reg arready_next;
 reg rvalid_next;
+reg rlast_next;
 
 reg [31:0]rdata;
 reg [31:0]rdata_next;
@@ -128,6 +129,7 @@ always_comb begin
 	trid_next = trid;
 	arready_next = 0;
 	rvalid_next = 0;
+	rlast_next = 0;
 	rd_next = 0;
 	case (rstate)
 	R_ADDR: if (s.arvalid) begin
@@ -143,6 +145,7 @@ always_comb begin
 			// present address and rd to register file
 			rstate_next = R_DATA;
 			rvalid_next = 1;
+			rlast_next = 1;
 			rdata_next = i_rdata;
 		end
 	R_DATA: if (s.rready) begin
@@ -151,6 +154,7 @@ always_comb begin
 			arready_next = 1;
 		end else begin
 			rvalid_next = 1;
+			rlast_next = 1;
 		end
 	endcase
 end
@@ -169,6 +173,7 @@ always_ff @(posedge clk) begin
 	trid <= trid_next;
 	s.arready <= arready_next;
 	s.rvalid <= rvalid_next;
+	s.rlast <= rlast_next;
 	o_rreg <= rreg_next;
 	o_rd <= rd_next;
 end