commit 071a08bb2b8bfdd304142613b37e5d6664df99b3 parent f80821a6e8e1a537fb85f49f9f259958afa4d7fe Author: Brian Swetland <swetland@frotz.net> Date: Thu, 9 Feb 2012 17:47:11 -0800 de0nano: update project file Diffstat:
| M | de0nano/de0nano.qsf | | | 24 | +++++++++++++----------- |
1 file changed, 13 insertions(+), 11 deletions(-)
diff --git a/de0nano/de0nano.qsf b/de0nano/de0nano.qsf @@ -222,16 +222,6 @@ set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_RO set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD OFF -set_global_assignment -name VERILOG_FILE ../verilog/control.v -set_global_assignment -name TEXT_FILE fw.txt -set_global_assignment -name VERILOG_FILE ../verilog/regfile.v -set_global_assignment -name VERILOG_FILE ../verilog/library.v -set_global_assignment -name VERILOG_FILE ../verilog/cpu32.v -set_global_assignment -name VERILOG_FILE ../verilog/alu.v -set_global_assignment -name VERILOG_FILE ../verilog/uart.v -set_global_assignment -name VERILOG_FILE de0nano.v -set_global_assignment -name VERILOG_FILE aram.v -set_global_assignment -name SDC_FILE de0nano.sdc set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation @@ -244,4 +234,15 @@ set_global_assignment -name EDA_TEST_BENCH_NAME testbench -section_id eda_simula set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id testbench set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME testbench -section_id testbench set_global_assignment -name EDA_TEST_BENCH_FILE testbench.v -section_id testbench -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top + +set_global_assignment -name VERILOG_FILE ../verilog/ram.v +set_global_assignment -name VERILOG_FILE ../verilog/control.v +set_global_assignment -name TEXT_FILE fw.txt +set_global_assignment -name VERILOG_FILE ../verilog/regfile.v +set_global_assignment -name VERILOG_FILE ../verilog/library.v +set_global_assignment -name VERILOG_FILE ../verilog/cpu32.v +set_global_assignment -name VERILOG_FILE ../verilog/alu.v +set_global_assignment -name VERILOG_FILE ../verilog/uart.v +set_global_assignment -name VERILOG_FILE de0nano.v +set_global_assignment -name SDC_FILE de0nano.sdc +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +\ No newline at end of file