cpu32

commit f80821a6e8e1a537fb85f49f9f259958afa4d7fe
parent cac7e935da231e70b43021e547e101e83f8ac6d5
Author: Brian Swetland <swetland@frotz.net>
Date:   Thu,  9 Feb 2012 17:46:11 -0800

cpu32/control: don't expose uninteresting signals

Diffstat:
M
verilog/control.v
 | 
5
+++--
M
verilog/cpu32.v
 | 
4
----

2 files changed, 3 insertions(+), 6 deletions(-)
diff --git a/verilog/control.v b/verilog/control.v
@@ -8,12 +8,13 @@ module control (
 	output ctl_d_or_b,
 	output ctl_branch,
 	output ctl_branch_ind,
-	output ctl_ram_op,
 	output ctl_imm16,
-	output ctl_link_bit,
 	output [3:0] ctl_alu_func
 	);
 
+wire ctl_ram_op;
+wire ctl_link_bit;
+
 // cheesy decoder -- TODO: write for real
 assign ctl_regs_we = 
 	(opcode[3:1] == 3'h0) ||
diff --git a/verilog/cpu32.v b/verilog/cpu32.v
@@ -34,8 +34,6 @@ wire ctl_regs_we;    // 1 = write back to register file
 wire ctl_d_or_b;     // 0 = write to R[opseld], 1 = R[opselb]
 wire ctl_branch;     // 1 = direct branch
 wire ctl_branch_ind; // 1 = indirect branch
-wire ctl_link_bit;   // 1 if the link bit is set (only for branches)
-wire ctl_ram_op;
 wire ctl_imm16;      // 0 = bdata, 1 = imm16 -> alu right
 wire [3:0] ctl_alu_func;
 wire ctl_ram_we;
@@ -49,11 +47,9 @@ control control(
 	.ctl_d_or_b(ctl_d_or_b),
 	.ctl_branch(ctl_branch),
 	.ctl_branch_ind(ctl_branch_ind),
-	.ctl_ram_op(ctl_ram_op),
 	.ctl_imm16(ctl_imm16),
 	.ctl_ram_we(ctl_ram_we),
 	.ctl_ram_rd(ctl_ram_rd),
-	.ctl_link_bit(ctl_link_bit),
 	.ctl_alu_func(ctl_alu_func)
 	);