cpu32

commit 0ce0f1485385e95fd38d5db6e69d69d6521021a5
parent bb574c9e14523d9fb34f26a1a97903e1583d8af2
Author: Brian Swetland <swetland@frotz.net>
Date:   Sat, 18 Feb 2012 05:29:23 -0800

dualsyncram: update this so that quartus can infer memory correctly

Diffstat:
M
verilog/dualsyncram.v
 | 
19
+++++++++++--------
M
verilog/testbench.v
 | 
6
++----

2 files changed, 13 insertions(+), 12 deletions(-)
diff --git a/verilog/dualsyncram.v b/verilog/dualsyncram.v
@@ -4,15 +4,15 @@
 
 module dualsyncram #(parameter DWIDTH=16, parameter AWIDTH=8) (
 	input clk,
-	input [AWIDTH-1:0] a_waddr,
+	input [AWIDTH-1:0] a_addr,
 	input [DWIDTH-1:0] a_wdata,
 	input a_we,
-	input [AWIDTH-1:0] b_waddr,
+	input [AWIDTH-1:0] b_addr,
 	input [DWIDTH-1:0] b_wdata,
 	input b_we,
-	input [AWIDTH-1:0] a_raddr,
+	//input [AWIDTH-1:0] a_raddr,
 	output reg [DWIDTH-1:0] a_rdata,
-	input [AWIDTH-1:0] b_raddr,
+	//input [AWIDTH-1:0] b_raddr,
 	output reg [DWIDTH-1:0] b_rdata
 	);
 
@@ -20,11 +20,14 @@ reg [DWIDTH-1:0] mem[0:2**AWIDTH-1];
 
 always @(posedge clk) begin
 	if (a_we)
-		mem[a_waddr] <= a_wdata;
+		mem[a_addr] <= a_wdata;
+	a_rdata <= mem[a_addr];
+end
+
+always @(posedge clk) begin
 	if (b_we)
-		mem[b_waddr] <= b_wdata;
-	a_rdata <= mem[a_raddr];
-	b_rdata <= mem[b_raddr];
+		mem[b_addr] <= b_wdata;
+	b_rdata <= mem[b_addr];
 end
 
 endmodule
diff --git a/verilog/testbench.v b/verilog/testbench.v
@@ -36,14 +36,12 @@ cpu32 cpu(
 
 dualsyncram #(32,12) memory(
 	.clk(clk),
-	.a_raddr(romaddr[13:2]),
+	.a_addr(romaddr[13:2]),
 	.a_rdata(romdata),
-	.a_waddr(12'b0),
 	.a_wdata(32'b0),
 	.a_we(1'b0),
-	.b_raddr(ramaddr[13:2]),
+	.b_addr(ramaddr[13:2]),
 	.b_rdata(ramrdata),
-	.b_waddr(ramaddr[13:2]),
 	.b_wdata(ramwdata),
 	.b_we(ramwe)
 	);