cpu32

commit 28a2fb2465673e397897f70005023f101373788d
parent 1c3b287b3efbec89618335aa43a71ee23f74d046
Author: Brian Swetland <swetland@frotz.net>
Date:   Sat, 18 Feb 2012 03:27:20 -0800

dualsyncram: dual-ported sync sram

Diffstat:
A
verilog/dualsyncram.v
 | 
30
++++++++++++++++++++++++++++++

1 file changed, 30 insertions(+), 0 deletions(-)
diff --git a/verilog/dualsyncram.v b/verilog/dualsyncram.v
@@ -0,0 +1,30 @@
+// Copyright 2012, Brian Swetland
+
+`timescale 1ns/1ns
+
+module dualsyncram #(parameter DWIDTH=16, parameter AWIDTH=8) (
+	input clk,
+	input [AWIDTH-1:0] a_waddr,
+	input [DWIDTH-1:0] a_wdata,
+	input a_we,
+	input [AWIDTH-1:0] b_waddr,
+	input [DWIDTH-1:0] b_wdata,
+	input b_we,
+	input [AWIDTH-1:0] a_raddr,
+	output reg [DWIDTH-1:0] a_rdata,
+	input [AWIDTH-1:0] b_raddr,
+	output reg [DWIDTH-1:0] b_rdata
+	);
+
+reg [DWIDTH-1:0] mem[0:2**AWIDTH-1];
+
+always @(posedge clk) begin
+	if (a_we)
+		mem[a_waddr] <= b_wdata;
+	if (b_we)
+		mem[b_waddr] <= b_wdata;
+	a_rdata <= mem[a_raddr];
+	b_rdata <= mem[b_raddr];
+end
+
+endmodule