cpu32

commit 6fbf22d0e77f202b72c8716a5d9b28f0be6efbda
parent 54cd39dd4d480954fb922a54bf32d2d428ed5a9f
Author: Brian Swetland <swetland@frotz.net>
Date:   Sat, 18 Feb 2012 05:03:42 -0800

dualsyncram: typo

Diffstat:
M
verilog/dualsyncram.v
 | 
2
+-

1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/verilog/dualsyncram.v b/verilog/dualsyncram.v
@@ -20,7 +20,7 @@ reg [DWIDTH-1:0] mem[0:2**AWIDTH-1];
 
 always @(posedge clk) begin
 	if (a_we)
-		mem[a_waddr] <= b_wdata;
+		mem[a_waddr] <= a_wdata;
 	if (b_we)
 		mem[b_waddr] <= b_wdata;
 	a_rdata <= mem[a_raddr];