cpu32

commit 8ae00b58fb7ea682bfd0220314d1ba7826e6d9a3
parent 5ca444a707b76478337dbbd4f14eac0cc19c9683
Author: Brian Swetland <swetland@frotz.net>
Date:   Sun,  5 Feb 2012 14:24:30 -0800

uart: well, more of a uat just at the moment...

Diffstat:
A
verilog/uart.v
 | 
59
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
A
verilog/uart_tb.v
 | 
39
+++++++++++++++++++++++++++++++++++++++

2 files changed, 98 insertions(+), 0 deletions(-)
diff --git a/verilog/uart.v b/verilog/uart.v
@@ -0,0 +1,59 @@
+// Copyright 2012, Brian Swetland.  If it breaks, you keep both halves.
+
+`timescale 1ns/1ns
+
+module uart(
+	input clk,
+	input reset,
+	input [8:0] bdiv,
+	input [7:0] wdata,
+	input we,
+	output tx
+	);
+
+reg bclk;
+reg [8:0] bcnt;
+reg [7:0] thr;
+
+reg [7:0] tx_fifo;
+reg [10:0] tx_shift;
+wire tx_busy;
+reg tx_start;
+
+assign tx = tx_shift[0];
+
+assign tx_busy = (tx_shift[10:1] != 0);
+
+always @(posedge bclk, posedge reset) begin
+	if (reset)
+		tx_shift <= 11'h001;
+	else if (tx_busy) 
+		tx_shift = { 1'b0, tx_shift[10:1] };
+	else if (tx_start) begin
+		tx_shift <= { 1'b1, tx_fifo, 2'b01 };
+	end
+end
+
+always @(posedge clk) begin
+	if (reset) begin
+		bcnt <= 0;
+		bclk <= 0;
+		tx_start <= 0;
+	end else begin
+		if (bcnt == bdiv) begin
+			bcnt <= 9'h0;
+			bclk <= !bclk;
+		end else begin
+			bcnt <= bcnt + 1;
+			bclk <= bclk;
+		end
+		if (tx_busy)
+			tx_start <= 0;
+		else if (we) begin
+			tx_fifo = wdata;
+			tx_start <= 1;
+		end
+	end
+end
+endmodule
+
diff --git a/verilog/uart_tb.v b/verilog/uart_tb.v
@@ -0,0 +1,39 @@
+// Copyright 2012, Brian Swetland.  If it breaks, you keep both halves.
+
+`timescale 1ns/1ns
+
+module uart_tb ();
+
+reg clk;
+reg reset;
+
+uart uart0(
+	.wdata("A"),
+	.we(1),
+	.reset(reset),
+	.clk(clk),
+	.bdiv(434)
+	);
+
+initial begin
+	reset = 1;
+	#30 ;
+	reset = 0;
+end
+
+always begin
+	clk = 0;
+	#10 ;
+	clk = 1;
+	#10 ;
+end
+
+initial #1000000 $finish;
+
+initial begin
+        $dumpfile("uart.vcd");
+        $dumpvars(0,uart_tb);
+end
+
+endmodule
+