cpu32

commit d391047f775ac30eedaa55121306be9135862bfd
parent df7f05564ddf620edb5e44bdf61705f96449127e
Author: Brian Swetland <swetland@frotz.net>
Date:   Sun,  5 Feb 2012 10:35:51 -0800

regfile: don't initialize

Diffstat:
M
verilog/regfile.v
 | 
11
-----------

1 file changed, 0 insertions(+), 11 deletions(-)
diff --git a/verilog/regfile.v b/verilog/regfile.v
@@ -11,17 +11,6 @@ module regfile #(parameter DWIDTH=16, parameter AWIDTH=3) (
 
 reg [DWIDTH-1:0] R[0:2**AWIDTH-1];
 
-initial begin
-	R[0] <= 0;
-	R[1] <= 0;
-	R[2] <= 0;
-	R[3] <= 0;
-	R[4] <= 0;
-	R[5] <= 0;
-	R[6] <= 0;
-	R[7] <= 0;
- end
-
 always @ (posedge clk)
 	if (we)
 		R[wsel] <= wdata;