gateware

commit 04fd1dc2ee9722f0bb38817b560ae5286049e324
parent 0d4b06f5abe5edd5907c0485f7cdf568f1019cbc
Author: Brian Swetland <swetland@frotz.net>
Date:   Wed, 21 Nov 2018 13:04:19 -0800

build: build a vga testbench if you 'make vga'

Diffstat:
M
Makefile
 | 
33
+++++++++++++++++++++++----------
A
hdl/testvga.sv
 | 
40
++++++++++++++++++++++++++++++++++++++++
M
tests/runtest
 | 
2
+-

3 files changed, 64 insertions(+), 11 deletions(-)
diff --git a/Makefile b/Makefile
@@ -3,7 +3,9 @@ CPU_SRCS := hdl/cpu/cpu.v hdl/cpu/alu.v hdl/cpu/regfile.v
 
 VGA_SRCS := hdl/vga/vga40x30x2.v hdl/vga/vga.v hdl/vga/videoram.v hdl/vga/chardata.v
 
-VSIM_SRCS := hdl/testbench.sv hdl/simram.sv $(CPU_SRCS)
+VSIM_CPU_SRCS := hdl/testbench.sv hdl/simram.sv $(CPU_SRCS)
+
+VSIM_VGA_SRCS := hdl/testvga.sv $(VGA_SRCS)
 
 ICE40_SRCS := hdl/ice40.v hdl/spi_debug_ifc.v hdl/lattice/pll_12_25.v
 ICE40_SRCS += $(CPU_SRCS) $(VGA_SRCS)
@@ -16,14 +18,25 @@ NEXTPNR := nextpnr-ice40
 YOSYS := yosys
 ICEPACK := icepack
 
-VOPTS := --top-module testbench --Mdir out --exe ../src/testbench.cpp --cc -CFLAGS -DTRACE --trace
+VOPTS_CPU := --top-module testbench --Mdir out/cpu
+VOPTS_CPU += --exe ../src/testbench.cpp --cc -CFLAGS -DTRACE --trace
 
-all: out/Vtestbench out/ice40.bin out/a16 out/d16 out/icetool
+VOPTS_VGA := --top-module testbench --Mdir out/vga
+VOPTS_VGA += --exe ../src/testbench.cpp --cc -CFLAGS -DTRACE -CFLAGS -DVGA --trace
 
-out/Vtestbench: $(VSIM_SRCS) src/testbench.cpp
-	@mkdir -p out
-	@$(VERILATOR) $(VOPTS) $(VSIM_SRCS)
-	@make -C out -f Vtestbench.mk
+all: out/cpu/Vtestbench out/ice40.bin out/a16 out/d16 out/icetool
+
+vga: out/vga/Vtestbench
+
+out/cpu/Vtestbench: $(VSIM_CPU_SRCS) src/testbench.cpp
+	@mkdir -p out/cpu
+	@$(VERILATOR) $(VOPTS_CPU) $(VSIM_CPU_SRCS)
+	@make -C out/cpu -f Vtestbench.mk
+
+out/vga/Vtestbench: $(VSIM_VGA_SRCS) src/testbench.cpp
+	@mkdir -p out/vga
+	@$(VERILATOR) $(VOPTS_VGA) $(VSIM_VGA_SRCS)
+	@make -C out/vga -f Vtestbench.mk
 
 out/ice40.bin: out/ice40.asc
 	@mkdir -p out
@@ -59,8 +72,8 @@ out/ice40.asc: out/ice40.blif
 	$(ARACHNEPNR) -d 5k -p sg48 -o out/ice40.asc -p hdl/ice40up.pcf out/ice40.blif 2>&1 | tee out/ice40.pnr.log
 endif
 
-run: out/Vtestbench out/test.hex
-	./out/Vtestbench -trace out/trace.vcd -dump out/memory.bin -load out/test.hex
+run: out/cpu/Vtestbench out/test.hex
+	./out/cpu/Vtestbench -trace out/trace.vcd -dump out/memory.bin -load out/test.hex
 
 out/test.hex: src/test.s out/a16 out/d16
 	out/a16 src/test.s out/test.hex
@@ -80,7 +93,7 @@ out/icetool: src/icetool.c src/ftdi.c src/ftdi.h
 	@mkdir -p out
 	gcc -g -Wall -O1 -o out/icetool src/icetool.c src/ftdi.c -lusb-1.0 -lrt
 
-TEST_DEPS := out/Vtestbench out/a16 out/d16 tests/runtest
+TEST_DEPS := out/cpu/Vtestbench out/a16 out/d16 tests/runtest
 
 TESTS := $(sort $(wildcard tests/*.s))
 
diff --git a/hdl/testvga.sv b/hdl/testvga.sv
@@ -0,0 +1,40 @@
+// Copyright 2015, Brian Swetland <swetland@frotz.net>
+// Licensed under the Apache License, Version 2.0.
+
+`timescale 1ns / 1ps
+
+`define HEX_PATHS
+
+module testbench(
+        input clk,
+	output [3:0]vga_red,
+	output [3:0]vga_grn,
+	output [3:0]vga_blu,
+	output vga_hsync,
+	output vga_vsync,
+	output vga_frame
+        );
+
+wire [1:0]red;
+wire [1:0]grn;
+wire [1:0]blu;
+
+vga40x30x2 vga(
+	.clk25m(clk),
+	.red(red),
+	.grn(grn),
+	.blu(blu),
+	.hs(vga_hsync),
+	.vs(vga_vsync),
+	.fr(vga_frame),
+	.vram_waddr(11'b0),
+	.vram_wdata(8'b0),
+	.vram_we(1'b0),
+	.vram_clk(clk)
+	);
+
+assign vga_red = { red, red[0], red[0] };
+assign vga_grn = { grn, grn[0], grn[0] };
+assign vga_blu = { blu, blu[0], blu[0] };
+
+endmodule
diff --git a/tests/runtest b/tests/runtest
@@ -17,7 +17,7 @@ if ! ./out/a16 "$1" "out/$1.hex" ; then
 	exit 0
 fi
 
-if ! ./out/Vtestbench -trace "out/$1.vcd" -load "out/$1.hex" | grep '^:WRI' > "out/$1.log" ; then
+if ! ./out/cpu/Vtestbench -trace "out/$1.vcd" -load "out/$1.hex" | grep '^:WRI' > "out/$1.log" ; then
 	echo FAIL: Error simulating $1
 	echo FAIL > "out/$1.status"
 	exit 0